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| wdc the western design center, inc. w65c832 ., ') w65cb32 ~ information, speciflca~ion and da~a s ~~~ a ~#; b i 0 r p m r r r v v e v m h l q t d p s s d / i b y s a x 2 e 6 5 4 3 2 1 44 43 42 41 40 nmi- 7 39 e8/e16 vpa 8 38 r/w- vdd 9 37 vdd ao 10 36 do/a16 a1 11 35 d1/a17 vss 12 w65c832 34 d2/a18 a2 13 33 d3/a19 a3 14 32 d4/a20 a4 15 31 d5/a21 as 16 30 d6/a22 .. ',. a6 17 29 d7/a23 ) , 18 19 20 21 22 23 24 25 26 27 28 ~ a a a a v v a a a a 7 8 9 1 1 s s 1 1 1 1 0 1 s s 2 3 4 s march 1991 woc the western design center, inc. w65c832 woc reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. information contained herein is provided gratuitously and without liability, to any user. reasonable efforts have been made to verify the accuracy of the information but no guarantee whatsoever is given as to the accuracy or as to its applicability to particular uses. in every instance, it must be the responsibility of the user to determine the suitability of the products for each application. woc products are not authorized for use as critical components in life support devices or systems. nothing contained herein shall be construed as a recommendation to use any product in violation of existing patents or other rights of third parties. the sale of any woc product is subject to all wdc terms and conditions of. sales and sales policies, copies of which are available upon request. copyright (c) 1981-1990 by the western design center, inc. all rights reserved, including the right of reproduction in whole or in part in any form. march 1990 woc the western design center, inc. w6sc832 table of contents introduction 1 section 1 : w65c832 function description 2 1.1 instruction register and decode 2 1.2 timing control unit . . . 2 1.3 arithmetic and logic unit 2 1.4 internal registers .. . 2 1.5 accumulators .... . 3 1.6 data bank register. 3 1.7 direct ...... . 3 1.8 index . . . . . . . . 3 1.9 processor status .. . 3 1.10 program bank register 4 1.11 program counter . 4 1.12 stack pointer . . . . 4 section 2 : pin function description 10 2.1 abort . . .. .11 2.2 address bus ... . .11 2.3 bus enable ... . . . .11 2.4 data/address bus. .11 2.5 emulation status. .12 2.6 interrupt request .. 12 2.7 memory lock ... .12 2.8 memory/index select status. .12 2.9 non-maskable interrupt. .12 2.10 phase 2 in ..... .12 2.11 read/write ..?.. .13 2.12 ready . . . . . . . .13 2.13 reset . . . . . . . .13 2.14 valid data address, valid program address .14 2.15 vdd and vss .14 2.16 vector pull .... .14 section 3 : addressing modes 15 3.1 reset and interrupt vectors .15 3.2 stack ........ . .15 3.3 direct. . . . . . . .'. .15 3.4 program address space .15 3.5 data address space .... .15 march 1990 29 woc the western design center, inc. w65c832 section 4 : timing, ac and dc characteristics 24 4.1 absolute maximum ratings. .24 4.2 dc characteristics. .25 4.3 ac characteristics, 5v .. .26 4.4 ac characteristics, 1.2v. . .27 section 5 : ordering information section 6 : application information section 7 : assembler syntax standards 43 7.1 directives ...? .43 7.2 comments .... .43 7.3 the source line .43 section 8 : caveats 46 8.1 stack addressing ...... . .47 8.2 direct addressing ..... . .47 8.3 absolute indexed addressing. .48 < 8.4 abort. . . . . . . . . . . .48 8.5 vda and vpa ....... . .48 8.6 apple ii, iic, iic and 11+ disk systems .48 8.7 db/ba operation ....... . .49 8.8 m/x output. . . . . . . . . . . . . ... .49 8.9 all opcodes function in all modes of operation. .49 8.10 indirect jumps ................ . .49 8.11 switching modes ............... . .49 8.12 hardware interrupts, brk, and cop instructions. .50 8.13 binary mode. . . ... .50 8.14 wai instruction .50 8.15 stp instruction .50 8.16 cop signatures. .50 8.17 wdm opcode use. .50 8.18 roy pulled during write .. 51 8.19 mvn and mvp ...... . .51 8.20 interrupt priorities. . . . . . . . . . . .51 8.21 transfers from differing sized registers. .51 8.22 stack transfers. . . . . ... .51 8 .23 rep / sep . . . . . . . . . . . . . . . . . .51 march 1991 30 woc the western design center, inc. w65c832 table of contents tables section 1 : function description 2 1-1 w65c832 emulation and register width control. 9 section 2 : pin function description 10 2-1 pin function table. . . . . . .11 section 3 : addressing modes 15 3-1 address mode formats. .22 3-2 addressing mode summary .23 section 4 : timing, ac and dc characteristics 24 4-1 absolute maximum ratings ... . .24 4-2 dc characteristics ....... . .25 4-3a ac characteristics-5v, 4-7mhz . .26 4-3b ac characteristics-5v, 8-10mhz. .26 4-4a ac characteristics-1.2v, 40 khz .27 section 6: application information 30 6-1 instruction set . . . . . . . . . . . .30 6-2 vector locations .......... . .31 6-3 opcode matrix . . . . . . . . . . . . .32 6-4 operation, operation codes and status register. .33 6-5 instruction operation . . . . . 34-42 section 7 : assembler syntax standards 43 7-3-1 alternate mnemonics . . .44 7-3-2 byte selection operator .45 section 8: caveats 46 8-1 compatibility issues .....?............. 46-47 march 1990 wdc the western design center, inc. w65c832 table of contents figures section 1 : function description 2 1-1 internal architecture block diagram. . . . . 5 1-2 w65c832 native mode programming model . . . . . 6 1-3 w65c816 16-bit emulation programming model. 7 1-4 w65c02 8-bit emulation programming model. 8 1-5 w65c832 status register coding ...... . 9 section 2 : pin function description 10 2-1 w65c832 44 plcc pinout. . . . .10 section 4 : timing, ac and dc characteristics 24 4-1 timing diagram . . . . . . . . . . . . .28 march 1990 wdc the western design center, inc. w65c832 introduction the wdc w65c832 is a cmos 32-bit microprocessor featuring total software compatibility with their 8-bit nmos and 8-bit and 16-bit cmos 6500-series predecessors. the w65c832 is pin-to-pin compatible with 16-bit devices currently available. these devices offer the many advantages of cmos technology i including increased noise immunity, higher reliability, and greatly reduced power requirements. a software switch determines whether the processor is in the 8-bit or 16-bit "emulation" mode, or in the native mode, thus allowing existing systems to use the expanded features. as shown in the processor programming model, the accumulator, alu, x and y index registers have been extended to 32 bits. a 16-bit program counter, stack pointer and direct page register augments the direct page addressing mode (formerly zero page addressing). separate program bank and data bank registers allow 24-bit memory addressing with segmented or linear addressing for program space and 32-bit 4gbyte data space for asic use although only 24 bits of address are available in the standard pin-out. four signals provide the system designer with many options. the abort input can interrupt the currently executing instruction without modifying internal register, thus allowing virtual memory system design. valid data address (vda) and valid program address (vpa) outputs facilitate dual cache memory by indicating w.hether a data segment or program segment is accessed. modifying a vector is made easy by monitoring the vector pull (vp) output. \ key features of the w65c832 advanced cmos design for low power * separate program and data bank * power consumption and increased registers allow program noise immunity segmentation or full 16-mbyte * single 1.2-5.25v power supply, linear addressing as specified * new direct register and stack emulation mode allows complete relative addressing provides * hardware and software capability for re-entrant, compatibility with w65c816 designs re-cursive and re-iocatable 24-bit address bus allows access programming * to 16 mbytes of memory space * 24 addressing modes-13 original * full 32-bit alu, accumulator, 6502 modes, plus 11 new addressing and index registers modes with 91 instructions using * valid data address (vda) and 255 opcodes valid program address (vpa) * wait-for-interrupt (wai) and output allows dual cache and stop-the clock (stp) instructions cycle steal dma implementation further reduce power consumption, * vector pull (vp) output indicates decrease interrupt latency and when interrupt vectors are being allows synchronization with addressed. may be used to external events implement vectored interrupt * co-processor (cop) instruction design with associated vector supports abort (abort) input and associated co-processor configurations, i.e., * vector supports virtual memory floating point processors system design * block move ability march 1990 1 wdc the western design center, inc. w65c832 section 1 w65c832 function description the w65c832 provides the design engineer with upward mobility and software compatibility in applications where a 32-bit system configuration is desired. the w65c832's 32-bit hardware configuration, coupled with current software allows a wide selection of system applications. in the emulation mode, the w65c832 offers many advantages, including full software compatibility with 6502, w65c02 or w65c816 coding. in addition, the w65c832' s powerful instruction set and addressing modes make it an excellent choice for new 32-bit designs. internal organization of the w65c832 can be divided into two parts: 1) the register section and 2) the control section. instructions (or opcodes) obtained from program memory are executed by implementing a series of data transfers within the register section. signals that cause data transfers to be executed are generated within the control section. the w65c832 has a 32-bit internal architecture with an 8-bit external data bus. 1.1 instruction register and decode an opcode enters the processor on the data bus, and is latched into the instruction register during the instruction fetch cycle. this instruction is then decoded, along with timing and interrupt signals, to generate the various instruction register control signals. 1.2 timing control unit (tcu) the timing control unit keeps track of each instruction cycle as it is executed. the tcu is set to zero each time an instruction fetch is executed, and is advanced at the beginning of each cycle for as many cycles as is required to complete the instruction. each data transfer between registers depends upon decoding the contents of both the instruction register and the timing control unit. 1.3 arithmetic and logic unit (alu) all arithmetic and logic operations take place within the 32-bit alu. in addition to data operations, the alu also calculates the effective address for relative and indexed addressing modes. the result of a data operation is stored in either memory or an internal register. carry, negative, overflow and zero flags may be updated following the alu data operation. 1.4 internal registers (refer to programming model) march 1990 2 woc the western design center, inc. w65c832 1.5 accumulator the accumulator is a general purpose register which stores one of the operands, or the result of most arithmetic and logical operations. in the native mode the accumulator can be 8-, 16- or 32-bits wide. 1.6 data bank register (dbr) during modes of operation, the 8-bit data bank register holds the default bank address for memory transfers. the 24-bit address is composed of the 16-bit instruction effective address and the 8-bit data bank address. the register value is multiplexed with the data value and is present on the data/address lines during the first half of a data transfer memory cycle for the w65c832. the data bank register is initialized to zero during reset. 1.7 . direct (d) the 16-bit direct register provides an address offset for all instructions using direct addressing. the effective bank zero address is formed by adding the 8-bit instruction operand address to the direct register. the direct register is initialized to zero during reset. 1.8 index (x and y) there are two index registers (x and y) which may be used as general purpose registers or to provide an index value for calculation of the effective address. when executing an instruction with indexed addressing, the microprocessor fetches the opcode and the base address, and then modifies the address by adding the index register contents to the address prior to performing the desired operation. pre-indexing or post-indexing of indirect addresses may be selected. in the native mode, both index registers are 32 bits wide (providing the index select bit (x) equals zero). if the index select bit (x) equals one, both registers will be 8 bits wide, and the high bytes if forced to zero. 1.9 processor status (p) the 8-bit processor status register contains status flags and mode select bits. the carry (c), negative (n), overflow (v), and zero (z) status flags serve to report the status of most alu operations. these status flags are tested by use of conditional branch instructions. the decimal (d), irq disable (i), memory/accumulator (m), and index (x) bits are used as mode select flags. these flags are set by the program to change microprocessor operations. the emulation (e8 and e16) select and the break (b) flags are accessible only through the processor status register. the emulation (e8) mode select flag is selected by the exchange carry and emulation bits (xce) instruction. the xfe instruction exchanges the emulation (e8 and e16) mode select flags with the overflow and carry flags. table 1, emulation and register width control, illustrates the features of the native and emulation modes. the m and x flags are always equal to one in the 8-bit emulation mode. when an interrupt occurs during the emulation mode, the break flag is written to stack memory as bit 4 of the processor status register. march 1990 3 wdc the western design center, inc. w65c832 1.10 program bank register (pbr) the 8-bit program bank register holds the bank address for all instruction fetches. the 24-bit address consists of the 16-bit instruction effective address and the 8-bit program bank address. the register value is multiplexed with the data value and presented on the data/address lines during the first half of a program memory read cycle. the program bank register is initialized to zero during reset. the phk instruction pushes the pbr register onto the stack. 1.11 program counter (pc) the 16-bi t program counter register provides the addresses which are used to step the microprocessor through sequential program instructions. the register is incremented each time an instruction or operand is fetched from program memory. 1.12 stack pointer (s) the stack pointer is a 16-bit register which is used to indicate the next available location in the stack memory area. it serves as the effective address in stack addressing modes as well as subroutine and interrupt processing. the stack pointer allows simple implementation of nested subroutines and multiple-level interrupts. during the emulation mode, the stack pointer high-order byte (sh) is always equal to one. the bank address for all stack operations is bank zero. march 1990 4 wdc the western design center, inc. w65c832 figure 1-1 w65c832 internal architecture simplified block diagram ao-a7 a8-a15 00-07 (602) n.n1ao-07/ba7181s) index x (3l. iii ts) i a :: a: .... ii. ... :::> ., x wdc the western design center, inc. w65c832 8 bits 8 bits 8 bits index and data registers x register y register y accumulator a address registers o iprogram bank i program counter pc ____________ iregister (pbr) 1 ________________________ __ o direct register d o stack pointer s o idata bank- o ____________ 1 register ______________________________ _ dbr status register status p figure 1-2 w65c832 native mode programming model march 1990 6 wdc the western design center, inc. w65c832 8 bits 8 bits 8 bits 8 bits index and data registers x register y register accumulator x y a address registers o 1 program bank 1 program counter ______ 1 register (pbr) 1 ____________ _ pc o direct register d o stack pointer s o idata bank o ______ 1 register ________________ _ dbr status register status p figure 1-3 w65c816 16-bit emulation programming model march 1990 7 x woc the western design center, inc. w65c832 8 bits 8 bits 8 bits index and data registers x register y register y accumulator a address registers o 1 program bank 1 program counter pc ______ 1 register (pbr) 1 ____________ _ o direct register d o iiistack pointer ------------_-- ___ --1_1_---------- o idata bank o __________ 1 register __________________ _ s dbr status register status p figure 1-4 w65c02 8-bit emulation programming model /' '\ march 1990 8 woc the western design center, inc. w65c832 i status reg. (p) i i lei i-i i 111 lei e16 - w65c816 emulation i 1611181 181 e8 - w65c02 emulation inivimixidiiizici i i i i i i i i i i i i i i i i i i i i i i i carry 1 = true -- zero 1 = result zero i i i i i i irq- disable 1 = disable i i i i i decimal mode 1 = true i i i i index reg. select i i i i i memory width select overflow 1 = true i negative 1 = neg. figure 1-5 w65c832 status register coding table 1-1 w65c832 emulation and register width control i a and x,y i memory loads, i loads, stores, i stores, pushes, i pushes, pulls, i and and i pulls address generation i i i i e16 e8 m x 0 0 0 0 16 32 w65c832 native i 0 0 0 1 16 8 w65c832 native i 0 0 1 0 8 32 w65c832 native i 0 0 1 1 8 8 w65c832 native i 0 1 0 0 32 32 w65c832 native i 0 1 0 1 32 8 w65c832 native i 0 1 1 0 8 32 w65c832 native i 0 1 1 1 8 8 w65c832 native i 1 0 0 0 16 16 w65c816 emulation i 1 0 0 1 16 8 w65c816 emulation i 1 0 1 0 8 16 w65c816 emulation i 1 0 1 1 8 8 w65c816 emulation i 1 1 1 brk 8 8 w65c02 emulation i i march 1990 9 woc the western design center, inc. w65c832 section 2 pin function description a b i 0 r p m r r r v v e v m h l q t d y p s s s d a / x i 2 b e 6 5 4 3 2 1 44 43 42 41 40 nmi- 7 39 e8/e16 vpa 8 38 r/w- vdd 9 37 vdd ao 10 36 do/a16 a1 11 35 d1/a17 vss 12 w65c832 34 d2/a18 a2 13 33 d3/a19 a3 14 32 d4/a20 a4 15 31 d5/a21 as 16 30 d6/a22 a6 17 29 d7/a23 18 19 20 21 22 23 24 25 26 27 28 a a a a a v v a a a a 7 8 9 1 1 s s 1 1 1 1 0 1 s s 2 3 4 5 figure 2-1 w65c832 44 pin plcc pinout march 1990 10 wdc the western design center, inc. w65c832 table 2-1 pin function table pin description ao-a15 address bus abort- abort input be bus enable phi2(in) phase 2 in clock do/a16-d7/a23 data bus/address bus e8/el6 emulation select irq- interrupt request ml- memory lock m/x mode select (pm or px) nmi- non-maskable interrupt roy ready res- reset r/w- read/write vda valid data address vp- vector pull vpa valid program address vdd positive power supply (+5 volts) vss internal logic ground 2.1 abort (abort-) the abort input is used to abort instructions (usually due to an address bus condition). a negative transition will inhibit modification of any internal register during the current instruction. upon completion of this instruction, an interrupt sequence is initiated. the location of the aborted opcode is stored as the return address in stack memory. the abort vector address is 00fff8,9 (emulation mode) or 00ffe8,9 (native mode). note that abort- is a pulse-sensitive signal; i.e., an abort will occur whenever there is a negative pulse (or level) on the abort- pin during a phi2 clock. 2.2 address bus (ao-a15) these sixteen output lines form the low 16 bits of the address bus for memory and i/o exchange on the data bus. the address lines may be set to the high impedance state by the bus enable (be) signal. 2.3 bus enable (be) the bus enable input signal allows external control of the address and data buffers, as well as the r/w- signal. with bus enable high, the r/w- and address buffers are active. the data/address buffers are active during the first half of every cycle and the second half of a write cycle. when be is low, these buffers are disabled. bus enable is an asynchronous signal. 2.4 data/address bus (do/a16-d7/a23) these eight lines multiplex address bits al6-a23 with the data value do-d7. the address is present during the first half of a memory cycle, and the data value is read or written during the second half of the memory cycle. four memory cycles are required to transfer 32-bit values. these lines may be set to the high impedance state by the bus enable (be) signal. march 1990 11 wdc the western design center, inc. w65cs32 2.5 emulation status (es/e16) the emulation status output es/e16 reflects the state of the emulation es and e16 mode flags in the processor status (p) register. this signal may be thought of as an opcode extension and used for memory and system management. 2.6 interrupt request (irq-) the interrupt request input signal is used to request that an interrupt sequence be initiated. when the irq disable (i) flag is cleared, a low- input logic level initiates an interrupt sequence after the current instruction is completed. the wait-for-interrupt (wai) instruction may be executed to ensure the interrupt will be recognized immediately. the interrupt request vector address is oofffe,f (emulation mode) or ooffee, f (native mode). since irq- is a level-sensitive input, an interrupt will occur if the interrupt source was not cleared since the last interrupt. also, no interrupt will occur if the interrupt source is cleared prior to interrupt recognition. 2.7 memory lock (ml-) the memory lock output may be used to ensure the integrity of read-modify-write instructions in a multiprocessor system. memory lock indicates the need to defer arbitration of the next bus cycle. memory lock is low during the last three, five or nine cycles of asl, dec, inc, lsr, rol, ror, trb, and tsb memory referencing instructions, depending on the state of the m and es flags. 2.s memory/index select status (m/x) this multiplexed output reflects the state of the acctjinu-lator (m) and index (x) select flags (bits 5 and 4 of the processor status (p) register. flag m is valid during the phase 2 clock negative transition and flag x is valid during the phase 2 clock positive transition. these bits may be thought of as opcode extensions and may be used for memory and system management. 2.9 non-maskable interrupt (nmi-) a negative transition on the nmi- input initiates an interrupt sequence. a high-to-iow transition initiates an interrupt sequence after the current instruction is completed. the wait for interrupt (wai) instruction may be executed to ensure that the interrupt will be recognized immediately. the non-maskable interrupt vector address is oofffa,b (s-bit emulation mode), ooffea,b (16-bit emulation mode) or ooffda,b (native mode). since nmi- is an edge-sensitive input, an interrupt will occur if there is a negative transition while servicing a previous interrupt. also, no interrupt will occur if nmi- remains low. 2.10 phase 2 in (phi2) this is the system clock input to the microprocessor internal clock generator. during the low power standby mode, phi2 may held in the high or low state to preserve the contents of internal registers. however, usually it is held in the high state. march 1990 12 wdc the western design center, inc. w65c832 2.11 read/write (r/w-) when the r/w- output signal is in the high state, the microprocessor is reading data from memory or i/o. when in the low state, the data bus contains valid data from the microprocessor which is to be stored at the addressed memory location. the r/w- signal may be set to the high impedance state by bus enable (be). 2.12 ready (rdy) this bidirectional signal indicates that a wait for interrupt (wai) instruction has been executed allowing the user to halt operation of the microprocessor. a low input logic level will halt the microprocessor in its current state. returning rdy to the active high state allows the microprocessor to continue following the next phi2 clock negative transition. the rdy signal is internally pulled low following the execution of a wait for interrupt (wai) instruction, and then returned to the high state when a res-, abort-i nmi- 1 or irq- external interrupt is provided. this feature may be used to eliminate interrupt latency by placing the wai instruction at the beginning of the irq- servicing routine. if the irq- disable flag has been set l the next instruction will be executed when the irq- occurs. the processor will not stop after a wai instruction if rdy has been forced to a high state. however i this feature should only be used on asic's and the rdy buffer modified. the stop (stp) instruction has no effect on rdy. 2.13 reset (res-) the reset input is used to initialize the microprocessor and start program execution. the reset input buffer has hysteresis such that a simple r-c timing circuit may be used with the internal pullup device. the res- signal must be held low for at least two clock cycles after vdd reaches operating voltage. ready (rdy) has no effect while res- is being held low. during the reset conditioning period l the following period l the following processor initialization takes place: registers d 0000 sh = 01 dbr = 00 xh = 00 pbr 00 yh 00 n v/e16 m x d i z c/e8 i p = * */1 1 1 o 1 * */1 i * not _______________________________________ 1 initialized stp and wai instructions are cleared. signals e8 = 1 vda = 0 e16 = 1 vp- 1 m/x = 1 vpa = 0 r/w- 1 sync = 0 when reset is brought highl an interrupt sequence is initiated: o r/w- remains in the high state during the stack address cycles. o the reset vector address is oofffc/d. 13 march 1990 wdc the western design center, inc. w65c832 2.14 valid data address (vda) and valid program address (vpa) these two output signals indicate valid memory addresses when high logic 1, and are used for memory or iio address qualification. vda vpa o 0 internal operation-address and data bus available. the address bus may be invalid. o 1 valid program address-may be used for program cache control. 1 0 valid data address-may be used for data cache control. 1 1 opcode fetch-may be used for program cache control and single step control 2.15 vdd and vss vdd is the positive supply voltage and vss is system logic ground. 2.16 vector pull (vp-) the vector pull output indicates that a vector location is being addressed during an interrupt sequence. vp- is low during the last two interrupt sequence cycles, during which time the processor reads the interrupt vector. the vp- signal may be used to select and prioritize interrupts from several sources by modifying the vector addresses. march 1990 14 wdc the western design center, inc. w65c832 section 3 addressing modes the w65c832 is capable of directly addressing 16 mbytes of memory for program space and 4gbytes for data space although only 24 bits (16mbytes) of address space are available on the standard product. this address space has special significance within certain addressing modes, as follows: 3.1 reset and interrupt vectors the reset and interrupt vectors use the majority of the fixed addresses between ooffdo and ooffff. 3.2 stack the stack may use memory from 000000 to ooffff. the effective address of stack and stack relative addressing modes will be always be within this range. 3.3 direct the direct addressing modes are usually used to store memory registers and pointers. the effective address generated by direct, direct,x and direct,y addressing modes is always in bank 0 (oooooo-ooffff). 3.4 program address space the program bank register is not affected by the relative, relative long, absolute, absolute indirect, and absolute indexed indirect addressing modes or by incrementing the program counter from ffff. the only instructions that affect the program bank register are: rti, rtl, jml, jsl, and jmp absolute long. program code may exceed 64k bytes although code segments may not span bank boundaries. 3.5 data address space the data address space is contiguous throughout the 16 mbyte address space. words, arrays, records, or any data structures may span 64 kbyte bank boundaries with no compromise in code efficiency. the following addressing modes generate 24-bit effective addresses in w65c816 emulation mode and some, where noted by (*), generate 32-bit effective address in w65c832 native mode. o direct indexed indirect (d,x) * direct indirect indexed (d),y o direct indirect (d) o direct indirect long [dl * direct indirect long indexed [dl,y o absolute a * absolute a,x * absolute a,y o absolute long al * absolute long indexed al,x * stack relative indirect indexed (d,x),y march 1990 15 wdc the western design center, inc. w65c832 the following addressing mode descriptions provide additional detail as to how effective addresses are calculated. twenty-four addressing modes are available for the w65c832. the 32-bit indexed addressing modes are used with the w65c832i however, the high byte of the address is not available to the hardware on the standard w65c832 but is available on the core for asic's. detailed descriptions of the 24 addressing modes are as follows: 3.5.1 immediate addressing-f the operand is the second byte in 8-bit mode, second and third bytes when in the 16-bit mode, or 2nd thru 5th bytes in 32-bit mode of the instruction. 3.5.2 absolute-a with absolute addressing the second and third bytes of the instruction form the low-order 16 bits of the effective address. the data bank register contains the high-order 8 bits of the operand address. instruction: opcode addrl addrh operand address: dbr addrh addrl 3.5.3 absolute 1ong-al instruction: opcode addrl addrh baddr i operand address: baddr addrh addrl 3.5.4 direct-d the second byte of the instruction is added to the direct register (d) to form the effective address. an additional cycle is required when the direct register is not page aligned (01 not equal 0). the bank register is always o. instruction: opcode i offset i i direct register operand + i offset i address: 00 leffective address i 3.5.5 accumulator-a this form of addressing always uses a single byte instruction. the operand is the accumulator. 3.5.6 implied-i implied addressing uses a single byte instruction. the operand is implicitly defined by the instruction. march 1990 16 vidc the western design center i inc. w65c832 * 3.5.7 * 3.5.8 3.5.9 direct indirect indexed-(d)/y this address mode is often referred to as indirectly' the second byte of the instruction is added to the direct register (d). the 16-bit contents of this memory location is then combined with the data bank register to form a 24-bit base address. the y index register is added to the base address to form the effective address. in native mode this creates 32-bit effective addresses. instruction: opcode i offset i 1 direct register + i offset 00 i direct address then: 1 1 00 (direct address) +1 dbr 1 1 base address operand + 1 i y reg address: i effective address direct indirect long indexed-[d]/y with this addressing model the 24-bit base address is pointed to by the sum of the second byte of the instruction and the direct register. the effective address is this 24-bit base address plus the y index register. in native mode this creates 32-bit effective addresses. instruction: oecode 1 offset 1 1 direct register + i offset 00 i . direct address then: 1 (direct address) +1 dbr i i base address operand + i 1 y reg address: 1 effective address direct indexed indirect-(d,x) this address mode is often referred to as indirect, x. the second byte of the instruction is added to the sum of the direct register and the x index register. the result points to the low-order 16 bits of the effective address. the data bank register contains the high-order 8 bits of the effective address. instruction: oecode 1 offset 1 i direct register + i offset i direct address +1 x reg 1 00 i address then: 1 00 1 (address) operand +1 dbr 1 address: i effective address march 1990 17 woc the western design center, inc. w65c832 3.5.10 direct indexed with x-d,x the second byte of the instruction is added to the sum of the direct register and the x index register to form the 16-bit effective address. the operand is always in bank o. instruction: opcode 1 offset 1 1 direct register + 1 offset 1 direct address operand + 1 1 x reg 1 address: 00 leffective address 1 1 3.5.11 direct indexed with y-d,y the second byte of the instruction is added to the sum of the direct register and the y index register to form the 16-bit effective address. the operand is always in bank o. instruction: opcode 1 offset i i direct register + i offset 1 direct address operand + 1 1 y reg 1 address: 1 00 leffective address 1 * 3.5.12 absolute indexed with x-a,x the second and third bytes of the instruction are added to the x index register to form the low-order 16-bits of the effective address. the data bank register contains the high-order 8 bits of the effective address. in native mode this creates 32-bit effective addresses. instruction: opcode r addrl i addrh dbr i addrh 1 addrl operand +1 1 x reg address: 1 effective address * 3.5.13 absolute long indexed with x-al,x the second, third and fourth bytes of the instruction form a 24-bit base address. the effective address is the sum of this 24-bit address and the x index register. in native mode this creates 32-bit effective addresses. instruction: opcode i addrl 1 addrh baddr 1 baddr 1 addrh i addrl operand + i i x reg address: effective address 1 * 3.5.14 absolute indexed with y-a,y the second and third bytes of the instruction are added to the y index register to form the low-order 16 bits of the effective address. the data bank register contains the high-order 8 bits of the effective address. in native mode this creates 32-bit effective addresses. instruction: opcode 1 addrl 1 addrh dbr i addrh 1 addrl operand +1 1 y reg address: effective address march 1990 18 wdc the western design center, inc. w65c832 3.5.15 program counter relative-r this address mode, referred to as relative addressing, is used only with the branch instructions. if the condition being tested is met, the second byte of the instruction is added to the program counter, which has been updated to point to the opcode of the next instruction. the offset is a signed a-bit quantity in the range from -128 to 127. the program bank register is not affected. 3.5.16 program counter relative long-rl this address mode, referred to as relative long addressing, is usd only with the unconditional branch long instruction (brl) and the push effective relative instruction (per). the second and third bytes of the instruction are added to the program counter, which has been updated to point to the opcode of the next instruction. with the branch instruction, the program counter is loaded with the result. with the push effective relative instruction, the result is stored on the stack. the offset is a signed 16-bit quantity in the range from -32768 to 32767. the program bank register is not affected. 3.5.17 absolute indirect-{a) the second and third bytes of the instruction form an address to a pointer in bank o. the program counter is loaded with the first and second bytes at this pointer. with the jump long (jml) instruction, the program bank register is loaded with the third byte of the pointer. instruction: 1 opcode 1 addrl 1 addrh 1 indirect address = 1 00 i addrh i addrl new pc = (indirect address) with jml: new pc = (indirect address) new pbr = (indirect address +2) 3.5.18 direct indirect-(d) the second byte of the instruction is added to the direct register to form a pointer to the low-order 16 bits of the effective address. the data bank register contains the high-order 8 bits of the effective address. instruction: opcode 1 offset i i direct register + 1 offset 00 i direct address then: i 00 i (direct address) operand +1 dbr 1 ----~~~----~-------- address: i effective address 3.5.19 direct indirect long-[d] the second byte of the instruction is added to the direct register to form a pointer to the 24-bit effective address. instruction: opcode i offset i i direct register + i offset 00 i direct address then: operand (direct address) address: march 1990 19 wdc the western design center, inc. w65c832 3.5.20 absolute indexed indirect-(a,x) the second and third bytes of the instruction are added to the x index register to form a 16-::bit pointer in bank o. the contents of this pointer are loaded in the program counter. the program bank register is not changed. instruction: opcode addrl i addrh addrh i addrl i x reg pbr address then: pc = (address) 3.5.21 stack-s stack addressing refers to all instructions that push or pull data from the stack, such as push, pull, jump to subroutine, return from subroutine, interrupts, and return from interrupt. the bank address is always o. interrupt vectors are always fetched from bank o. 3.5.22 stack relative-d,s the low-order 16 bits of the effective address is formed from the sum of the second byte of the instruction and the stack pointer. the high-order 8 bits of the effective address is always zero. the relative offset is an unsigned 8-bit quantity in the range of 0 to 255. instruction: opcode i offset i i stack pointer operand + i offset i address: i 00 leffective address i * 3.5.23 stack relative indirect indexed-(d,s),y the second byte of the instruction is added to the stack pointer to form a pointer to the low-order 16-bit base address in bank o. the data bank register contains the high-order 8 bits of the base address. the effective address is the sum of the 24-bit base address and the y index register. in the native mode this creates 32-bit effective addresses. instruction: opcode i offset i 1 stack pointer + i offset 00 i s + offset then: i s + offset +1 dbr i i base address operand + i i y reg address: i effective address 20 march 1990 wdc the western design center, inc. w65c832 3.5.24 block source bank, destination bank-xya this addressing mode is used by the block move instructions. the second byte of the instruction contains the high-order 8 bits of the destination address. the y index register contains the low-order 16 bits of the destination address. the third byte of the instruction contains the high-order 8 bits of the source address. the x index register contains the low-order bits of the source address. the accumulator contains one less than the number of bytes to move. when the accumulator is zero it will move one byte. the second byte of the block move instructions is also loaded into the data bank register. in w65c832 native mode this x index register contains the entire source address and the x index register contains the entire destination address; therefore, the instruction is shorter by two bytes and two cycles per byte moved. instruction: i opcode dstbnk i srcbnk i source dstbnk -> dbr address: srcbnk i x reg destination dbr i y reg address: increment (mvn) or decrement (mvp) x and y. decrement c (if greater than zero), then pc+3->pc. * in w65c832 native mode these addressing modes creates 32-bit effective data space addresses. march 1990 21 wdc the western design center 1 inc. w65c832 table 3-1 address mode formats addressing mode immediate absolute absolute long direct page accumulator implied addressing direct indirect indexed direct indirect indexed long direct indexed indirect direct indexed by x direct indexed by y absolute indexed by x format #d #a tal #ext # (! a) ( tal) (ext) (d) ?a) ?al) ?ext) ~gll [>a ] [>ext] (d, x) ( ! d, x) (a, x) (!a,x) (! ai, x) (ext, x) (!ext,x) (no oqerand) (a,s),y ?d,s),y ?a, s) ,y ?al, s) y ?ext, s), y d,d d,a d,al d,ext a,d a,a a,al aiext a ,d al,a al,al al,ext ext,d ext, a extral ext,ext note: the alternate ! (exclamation point) is used in place of the i (vertical bar) . march 1990 22 i woc the western design center, inc. w65c832 table 3-2 addressing mode summary i instruction times imemory utilization i in memory cycles lin number of program i i i sequence bytes address mode i original i new i original i new 18-bit nmos i w65c832 18-bit nmos i w65c832 6502 i 6502 i l. immediate 2 2 (3) i 2 i 2 (3) 2. absolute 4 (5) 4 (3,5) i 3 i 3 3. absolute long 5 (3) i i 4 4. direct 3 (5) 3(3,4,5)1 2 i 2 5. accumulator 2 2 i 1 i 1 6. implied 2 2 i 1 i 1 7. direct indirect indexed 5 (1) 5(1,3,4) i 2 i 2 (d) , y i i 8. direct indirect indexed 6(3,4) i i 2 i long (d],y i i i 9. direct indexed indirect 6 6(3,4) i 2 i 2 i (d, x) i 1 110. direct,x 4 (5) 4(3,4,5) i 2 i 2 ill. direct,y 4 4 (3, 4) i 2 i 2 112. absolute, x 4(1,5) 4(1,3,5)1 3 i 3 113. absolute long,x 5 (3) i i 4 114. absolute,y 4 (1) 4(1,3) 1 3 i 3 115. relative 2(1,2) 2(2) 1 2 1 2 116. relative lonsl 3(2) i 1 3 117. absolute indirect (jump) 5 5 i 3 i 3 118. direct indirect 5(3,4) i i 2 119. direct indirect long 6(3,4) i 1 2 120. absolute indexed indirect 6 i i 3 1 (jump) i 1 12l. stack 3-7 3-11 i 1-3 i 1-4 122. stack relative 4 (3) i i 2 123. stack relative indirect 7 (3) i i 2 i indexed i i 124. block move x,y,c (source, 7 (6) i i 3 (6) i destination, block i i i notes (these are indicated in parentheses) : 1. page boundary, add 1 cycle if page boundary is crossed when forming address. 2. branch taken, add 1 cycle if branch is taken. 3. 16 bit operation, add 1 cycle, add 1 byte for immediate. 32 bit operation, add 3 cycles, add 3 bytes for immediate. 4. direct register low (dl) not equal zero, add 1 cycle. 5. read-modify-write, add 2 cycles for 8-bit, add 4 cycles for 16-bit, add 8 cycles for 32-bit operation. 6. for w6sc832 native mode, subtract 2 cycles and 2 bytes. march 1990 23 , woc the western design center, inc. w65c832 section 4 timing, ac and dc characteristics 4.1 absolute maximum ratings: (note 1) table 4-1 absolute maximum ratings rating symbol 1 value _____________________ ------_1--------------- 1 supply voltage vdd 1 -0.3 to +7.0v input voltage vin 1-0.3 to vdd +0.3v operating temperature ta 1 0 oc to + 70 oc 1 storage temperature ts 1 -55 0 c to +150 o c 1 ________________ i 1 this device contains input protection against damage due to high static voltages or electric fields; however, precautions should be taken to avoid application of voltages higher than the maximum rating. notes: 1. exceeding these ratings may result in permanent damage. functional operation under these conditions is not implied. march 1990 24 wdc the western design center, inc. w65c832 4.2 dc characteristics: vdd = 5.0v +/- 5%, vss = ov, ta = ooc to +70oc table 4-2 dc characteristics i parameter 'symbol' min , max ,unit' ,input high voltage ,vih ,- -,- -,- -, i res-, rdy, irq-, data, be i' 2.0 ivdd+0.3' v , , phi2, nmi-, abort- i 10.9*vddivdd+0.31 v i i , i i i [input low voltage i vil i i i i res-, rdy, irq-, data, be i' -0.3 i 0.8 , v i i phi2, nmi-, abort- i' -0.3 10.1*vdd, v i , , i i [ i ,input leakage current (vin = 0.4 to 2.4) i lin [ i i i i res-, nmi-, irq-, be, abort- " -100' 1 i ua i , (internal pullup) i' i i , i rdy (internal pullup, open drain) i ,-100 i 10.. , ua , , phi2 ,lin , -1 , 1 , ua , i address, data, r/w-, (off state, be=o) i ,-10 i 10 , ua , i i , , , __ ioutput high voltage (ioh=-100ua) i voh, , , , data,address,r/w-,ml-,vp-,m/x,e8/e16' , i , , vda, vpa i '0.7 vdd i 'v i i , , , __ [output low voltage (101 = 1.6rna) ,vol, , , , data,address,r/w-,ml-,vp-,m/x,e8/e16 i , , , i vda,vpa i [ [0.4 [ v , i , [ [ [ 'supply current (no load) '[' [rna/mhz [ , i , , , , ,standby current (no load, data bus = vssi isb, i i , i orvdd i , , , , , res-,nmi-,irq-,so-,be,abort-,phi2=vdd), , i 1 i ua , , [ i i i i 'capacitance (vin=ov, ta=250c, f=2mhz), i , , [ i logic,phi2 i cin, ,10, pf i i address, data, r/w-(off state) i cts' i 15 i pf i , , , i [ [ march 1990 25 woc the western design center, inc. w65c832 4.3 general ac characteristics: vdd= 5.0v +/- 5%, vss= ov, ta= ooc to +70oc table 4-3a w65c832 general ac characteristics, 4-7mhz i i i 4 mhz i 5 mhz i 6 mhz i 7 mhz i i parameter isymbo~imin maxlminlmaxlmin maxi minimax i unit icycle time 1 tcyc 1250 dc 1200ldc 1165 dc 1140 dc 1 ns iclock pulse width low i tpwl .125 10 1.10110 .082 10 1.07 10 i us iclock pulse width high i tpwh 1125 11001 - 182 170 - i ns ifall time! rise time itf,tr i - 10 i - 110 i - 5 i - 5 i ns iao-a15 hold time i tah 110 - 110 i - 110 - 110 - i ns iao-a15 setup time i tads i - 75 i - 167 i - 60 i - 60 i ns ia16-a23 hold time i tbh 110 - 110 i - 110 - 110 - 1 ns ia16-a23 setup time i tbas 1 - 90 i - 177 i - 65 i - 55 i ns iaccess time i tacc 1130 - 11151 - 187 - 160 - i ns iread data hold time i tdhr 110 - 110 i - 110 - 110 - i ns iread data setup time 1 tdsr 130 - 125 i - 120 - 125 - i ns iwrite data delay time 1 tmds i - 70 i - 165 1 - 160 i - 55 i ns iwrite data hold time i tdhw 110 - 110 i - 110 1 - 110 i - i ns iprocessor control setup time 1 tpcs 130 i - 125 i - 120 1 - 120 i - i ns iprocessor control hold time i tpch 110 i - 110 i - 110 i - 110 i - i ns ie8/e16!mx output hold time i teh 110 i - 110 i - i 5 i - i 5 i - i ns ie8/e16!mx output setup time 1 tes 150 1 - 137 i - 125 i - 125 i - i ns icapacitive load *1 1 cext i - 11001 - 11001 - 135 i - 135 1 pf ibe to valid data *2 i tbvd i - 130 i - 130 1 - 130 i - 130 i ns table 4-3b w65c832 general ac characteristics, 8-10mhz parameter i 9 mhz 110 mhz i i iminlmaxlminlmaxlunitl c:icle time i tcyc 1110 dc 1100ldc ns clock pulse width low i tpwl .055 10 1.05110 us clock pulse width high i tpwh 162 i - 55 - 50 i - ns fall time, rise time itf,tr i - i 5 5 5 ns ao-a15 hold time 1 tah 110 i - 10 - 10 - ns ao-a15 setue time i tads i - 140 - 40 - 40 ns a16-a23 hold time i tbh 110 i - 10 - 10 - ns a16-a23 setup time i tbas i - 145 - 45 - 45 ns access time i tacc 170 i - 70 - 70 - ns read data hold time i tdhr 110 i - 10 - 10 - ns read data setue time i tdsr 115 1 - 15 - 15 - ns write data dela:i time i tmds i - 140 - 40 - 40 ns write data hold time i tdhw 110 i - 10 - 10 - ns processor control setup time i tpcs 115 i - 15 - 15 - ns processor control hold time i tpch 110 i - 10 - 10 - ns es/e16!mx output hold time i teh i 5 i - 5 i - 5 - ns es/e16,mx output setue time i tes 115 i - 15 i - 15 - ns caeacitive load *1 be to valid data i cext i tbvd i i - - 135 130 - - 135 130 i i - - 35 30 pf ns *1 applies to address! data, r/w *2 be to high impedence state is not testable but should be the same amount of time as be to valid data march 1990 26 wdc the western design center, inc. w65c832 4.4 general ac characteristics: vdd= 1.2v, vss= ov, ta= ooc to +70oc table 4-4a w65c832 general ac characteristics, 40 khz i i i 40 khz i i i parameter isymbollmin imaxlunit/ icycle time / tcyc 1 - 125 i us iclock pulse width low i tpwl 112.5113 i us iclock pulse width high i tpwh 112.51 - i us ifal1 time, rise time itf,tr i - 110 1 ns iao-a15 hold time i tar 110 i - i ns iao-a15 setup time i taos i - i 2 i us iaao-a23 hold time i tbh 110 i - i ns ia16-a23 setup time i tbas 1 - 1 2 i us iaccess time i tacc 135 ,-, us 'read data hold time i tdrr 1100 i - 1 ns iread data setup time i tdsr 11.5 i - i us iwrite data delay time i tmds ,- i 2 i us iwrite data hold time i tdrw 110 i - i ns iprocessor control setup time i tpcs 11.5 i - i us jprocessor control hold time i tpch 1100 i - i ns ies/e16,mx output hold time i teh 110 i - 1 ns ie8/e16,mx output setup time i tes 1100 i - i ns icapacitive load *1 1 cext i - 11001 pf ibe to valid data *2 1 tbvd i - 130 1 ns *1 applied to address, data, r/w *2 be to high impedance state is not testable but should be the same amount of time as be to valid data 27 march 1990 woc the western design center, inc. w65cs32 1 <----------------tcyc2----------------> , ,<--tf phi 2 ___ ." , i i i / \1 1\ / 1\ tf-> ii <------tpwl------>, <------tpwh------> 1'----- tah-> , ,<- ->, irq-,nmi-,res-,---, i /-,-\/ roy , , \ , /\ i , - > -, <--:-t-=p=ch:::--- , i \ , 1/ \_, / tpcs-> i ,<- 1 m/x :m\/ \/x-,:x\/ \/m: :m\/ _/\ /\ i /\ ____ /\ /\ --- ----- 1-'-1 -> -i <--t-=e=h-- -> 1 <-teh 1->1 1 <-teh ->1 <-tes i tes->1 1<-1 i i , , 1 i i 1 es/e16 es\/-----:-\/e16-\/ \/e81-\/ /\ /\_,_/\ /\_,_/\_-- timing notes: 1. voltage levels are vl wdc the western design center, inc. w65c832 section 5 ordering information w 65c832 pl -8 =d~e7sc~r~1~'p~t~1~'o7n~ ___________________ 1 i i w-standard i i i i _p_r_od_u_c_t __ __ __ _________ i i_d_e_n_t_i_f_i_c_a_t_i_o_n n_umb e_r i i ~p~ac~k7a~g~e~~~~~~ __ 70 ______ _________ .- 1 pl-44 leaded plastic chip carrier temperature/processing blank- ooc to +70oc performance designator designators selected for speed and power. -4 4mhz -6 6mhz -8 8mhz -10 10mhz -e experimental general sales or technical assistance, and information about devices supplied to a custom specification may be requested from: the western design center, inc. 2166 east brown road mesa, arizona 85213 phone: 602-962-4545 fax: 602-835-6442 warning: mos circuits are subject to damage from static discharge internal static discharge circuits are provided to minimize part damage due to environmental static electrical charge build-ups. industry established recommendations for handling mos circuits include: 1. ship and store product in conductive shipping tubes or conductive foam plastic. never ship or store product in non-conductive plastic containers or non-conductive plastic foam material. 2. handle mos parts only at conductive work stations. 3. ground all assembly and repair tools. march 1990 29 wdc the western design center, inc. w65c832 section 6 application information table 6-1 w65c832 instruction set-alphabetical sequence adc and asl bcc bcs beq bit bmi bne bpl bra brk brl bvc bvs clc cld cli clv cmf cop cpx cpy dec dex dey eor inc inx iny jml jmp jsl jsr lda ldx ldy lsr mvn mvp nop ora pea pel per add memory to accumulator with carr~ "and memor with accumulator shift one b~t branch on carry clear (pc=o) branch on carry set (pc=l) branch if equal (pz=l) bit test branch if result minus (pn=l) branch if not equal (pz=o) branch if result plus (pn=o) branch always force break branch always long branch on overflow clear (pv=o) branch on overflow set (pv=l) clear carry flag clear decimal mode clear interrupt disable bit clear overflow flag compare memory and accumulator coprocessor compare memory and index x compare memory and index y decrement memory or accumulator by one decrement index x by one decrement index y by one "exclusive or" memory with accumulator increment memory or accumulator by one increment index x by one increment index y by one jump long jump to new location jump subroutine long jump' to new location saving return loaa accumulator with memory load index x with memory load index y with memory shift one bit right (memory or accumulator) block move negative block move positive no operation "or" memory with accumulator push effective absolute address on stack push effective absolute address on stack push effective program counter relative address on stack pha phb phd phk php phx phy pla plb pld plp plx ply rep rol ror rti rtl rts sbc sep sta stp stx sty stz tax tay tcd tcs tdc trb tsb tsc tsx txa txs txy tya tyx wai wdm xba xce xfe push accumulator on stack push data bank register on stack push direct register on stack push program bank register on stack push processor status on stack push index x on stack push index y on stack pull accumulator from stack pull data bank register from pull direct register from stack pull processor status from stack pull index x from stack pull index y from stack reset status bits rotate one bit left (memory or accumulator) rotate one bit right (memory or accumulator) return from interrupt return from subrout~ne long return from subroutine subtract memory from accumulator with borrow set processor status bite store accumulator in memory stop the clock store index x in memory store index y in memory store zero in memory transfer accumulator to index x transfer accumulator to index y transfer c accumulator to direct register transfer c accumulator to stack pointer register transfer d~rect register to c accumulator test and reset bit test and set bit transfer stack pointer register to c accumulator transfer stack pointer register to index x transfer index x to accumulator transfer index x to stack pointer register transfer index x to index y transfer index y to accumulator transfer index y to index x wait for interrupt reserved for future use exchange b and a accumulator exchange carry and emulation e8 exchange carry and emulation e8 and exchange overflow and emulation e16 for alternate mnemonics, see table 7-3-1. march 1990 30 wdc the western design center, inc. w65c832 table 6-2 vector locations w6sc02 8- emulation w6sc816 16-bit emulation oofffe,f-irq-/brk hardware/software ooffee,f-irq- hardware oofffc,d-reset- hardware ooffec,d-(reserved) oofffa,c-nmi- hardware ooffea,b-nmi- hardware oofff8,9-abort- hardware ooffe8,9-abort-hardware oofff6,7-(reserved) ooffe6,7-brk software oofff4,s-cop software ooffe4,5-cop software w6sc832 native ooffde,f-irq- hardware ooffdc,d-(reserved) ooffda,b-nmi- hardware ooffd8,9-abort- hardware ooffd6,7-brk software ooffd4,s-cop software the vp output is low during the two cycles used for vector location access. when an interrupt is executed, d=o and 1=1 in status register p. march 1990 31 ------ wdc the western design center, inc. w65c832 table 6-3 opcode matrix 0 1 2 brks ora (d.x) cops 2 8 2 6 2*8 bpl r ora (d).y ora (d) i 2 2 2 5 i 2 - 5 -- .js"l a and (d,xl jsl al 3 6 2 6 4 *8 -.- ---_. 8mi r and (d).y and (d) 2 2 2 5 2-5 -- f--.- ! w~m rti s eor (d.x) 1 7 2 6 2*2 ---- --- bve r eor (d).y eon (til 2 2 2 5 2 -5 --- ,---- ~-- rts s adc (d,x) per 5 1 6 2 6 3*6 bvs r adc (d),y adc(d) 2 2 2 5 2-5 r- brar sta (d.x) brl rl 2-2 2 6 3*3 bccr sta (d).y sta (d) 2 2 2 6 2-5 loy ii lda (d,x) ldx 1/ 2 2 2 6 2 2 8gs r loa (d).y loa (01) 2 2 2 5 2-5 --.,-.--- cpy ~ emf' (d,x) rep # 2 ~ ~ 6 2*3 --_._- ~.--.---"- .. - -.--~- i 0 i"~?~ cmp idly cmp(d) 2 5 2-5 . __ ._._, -- ------ cp;( ii ssc l 6 7 8 9 a b . c' ie , l_ symbol addressing mode symbol addressing mode # immediate (d] direct indirect long a accumulator [d],y diwct indirect long indexed r pro'l'am ('ou"t~r relatiye a absolule rl prograr., counler relative long a.x absolute indexed (with x) i unpiled a,y absolule indexed (wilh v) s stack al absolute long d direct al,x absolute long indexed d,x direct indexed (with x) d,s stack relati", ci,y direct indexed (with v) (d,s).y stack relative indirect indexed (d) direct indirect (a) absolute indirect (tl,x) direct indexed indirect (a,x) absolute indexed indirect (d).y direct indirect indexed xyc block move op code matrix legend !instruction ac'dressing mnemonic * = new w65c816/802 opcqdes mode ? = new w65c02 opcodes base blank = nmos 6502 opcodes base no, bytes no, cycles 32 march 1990 wdc the western design center, inc. w65c832 table 6-4 operation, operation codes and status register mne- monic aoc and asl bcc bcs beq i bit bmi bne bpl bra brk brl bvc bvs clc clo cli clv cmp cop cpx cpy dec oex dey eor inc inx iny jml jmp jsl jsr loa lox loy lsr mvn mvp nop ora pea pel per pha phb phd phk php phx phy pla pl8 plo plp plx ply rep rol ror rti rtl rts sbc i sec sed sei sep i sta i stp stx sty stz tax tay tco tcs toc trb tsb tsc tsx txa txs txy tya tyx wai wom x8a xce ... ~ .. 'om' .. ii i ~ ~ ~ !!. .. .. 'ti '" - ." .. to- ftii .. ~ :!. .. operation 1 2 3 4 5 6 1 8 9 10 14 1 19 20 21 a+m+c a 69 60 6f 65 i i~~ 77 61 75 79 67 aaiiii-a 29 20 2f 25 37 21 35 39 32 27 c- ll~-o 010 06 oa 16 ie branch if =0 i 90 branch ifc = 1 eo branch if z = 1 fo aam(note 1) 89 2c 24 34 branch if n = 1 30 branch if z = 0 do branch if n = 0 10 branch always 80 break (note 2) 182 00 branch long always branch if v = 0 50 branch if v = 1 70 0 c 1 18 0-0 08, ooiof 0-1 ~~ i o-v ,01 ici a-m c9 co cf c5 01 05 09 02 c7 co-processor i 02 x-m eo ec e4 y-m co cc c4 decrement ce c6 3a 06 de x-l-x ca y-1 y 88 152 a"tm - a 49 40 4f 45 51 57 41 55 50 5f 59 47 increments ee e6 1a f6 fe x+ i-x e8 y + 1 - y c8 jump long to new loc. dc jump to new loc. 4c 5c 6c 7c jump long to su8. 22 jump to sub. 20 fc m-a a9 ad af as bl b7 a1 85 bo bf b9 .82 a7 m-x a2 ae a6 b6 be m-y ao ac a4 84 8c o - l1iklqj - c 410 46 4a 56 510 m - m negative m - m positive no operation ea avm a 09 00 of 05 11 17 01 15 10 if 19 12 07 mp<:'1. mpc.2 - ms-l.ms f4 s - 2 - s m(d). mid' 1) - ms 1. ms 04 s 2-s mpc + rl, mpc ... r' .. 1 ms -1. ms 62 s - 2 - s a-ms.s-l s i i i: obr - ms. s 1 s i i o-ms.ms i,s-2-s , 06 pbr - ms. s - 1 - s i 4b p-ms.s-l-s 08 x - ms. s 1 - s i i ~~ y-ms.s-l-s s'1 s. ms- a 68 s .1 s.ms- obr i ab s + 2 - s. ms -1. ms - 0 2b s+ 1 - s. ms p i ! i 128 s+i-s.ms x fa ~+i-s.ms y i 7a miip- p c2 41 -c...l 2e 26 2a i 36 3e c"c 6e 66 sa 76 7e rtrn 40 rtrn from sub. long 6b rtrn subroutine f71 el i f5 60 a-m-<;-a e9 ed ef e5 fl fo ff f9 f2 e7 1 c 38' 1 0 f8 1-1 78 mvp-p 'ez a-m 80 8f 85 91 97 81 95 90 9f 99 92 87, stop ( 1-2) db x-m 8e 88 96 v - m 8c 84 1 84 oo-m 9c 64 74 910 a-x aa a-y a8 c-o 5b c-s lb o-c 7b lc 14 avm-m oc 04 s-c 3b s-x ba x-a sa x-s 9a i x-v 9b v-a 96 v-x 8b o-roy c6 no operation (reserved) 42 8--a lob c-e fb processor '": status code mne- ... ~ 7 6 5 4 3 2 0 monic iii ~ 1 'ti jc n v m x 0 i z c e= 0 n v 1 b d i z ce 1 63 73 n v z c aoc 23 33 n z and n z c as .. bcc bcs beq m,m, z bit bmi bne bpl ? bra ? 0 i brk * 8rl 8vc 8vs 0 clc 0 clo 0 cli 0 clv c3 03 n z c cmp 0 i * cop n z c cpx n z c cpy n z dec n z oex n z dey 43 53 n z eor n z inc n z inx n z iny * jml jmp jsl n jsr a3 b3 z loa n z lox n z loy 0 z c lsr 54 * mvn 44 * mvp nop, 03 13 n z ora * pea * pel * per pha phb * phd * phk php ie phx ? phy n z pla ,n - z ',* plb 'n z 1* plo n v m x 0 i z :1 plp n z plx n z ply n v m x 0 i z rep in z ci rol n z c ror n v m x 0 i z c rti * rtl rts e3 f3 n v z c sbc 1 sec 1 sed 1 sei n v m x 0 i z c* sep 83 93 sta '. stp stx sty i. ? stz n tax in z tay n z * tco * tcs n i. * toc z ? trb z ? tsb n z * tsc n z tsx n z txa txs n z * txy n z tva n z * tyx ? wai * wom ! n z * xba e * xce i i ! ! i 3. * = new w65c6161802 instructions + add vor notes: ? = new w65c02 instructions - subtract. -v- exclusive or 1. bitimm i ten and v fla snotalfected. when m 0.m1 -nandm -v. woc the western design center, inc. w65c832 table 6-5 instruction operation (14) (14) (15 ) address mode cycle vp,ml,vda,vpa address bus data bus r/w 1. immediate-i 1. 1 1 1 1 pbr/pc opcode 1 (ldy,cpy,cpx,ldx,orai 2. 1 1 0 1 pbr,pc+l ido 1 and,eor/adc,bit/lda 1 (1) 2a. 1 1 0 1 pbr,pc+2-4 idl-3 1 cmp,sbc/rep,sep) (14 opcodes) (2, 3 and bytes) (2 1 3 and 5 cycles) 2a. absolute-a 1. 1 1 1 1 pbr/pc opcode 1 (bit,sty,stz/ldy, 2. 1 1 0 1 pbr / pc+l aal 1 ora, and, eor,adc 1 4. 1 1 1 0 dbr,aa byte 0 1/0 sta,lda/cmp/sbc) (1) 4a. 1 1 1 0 dbr,aa+1-3 bytesl-3 1/0 cpy,cpx,stx/ldx, 3. 1 1 0 1 pbr / pc+2 aah 1 (18 opcodes) (3 bytes) (4, 5 and 7 cycles 2b. absolute-(r-m-w)-a 1. 1 1 1 1 pbr,pc opcode 1 8 for 16-bit data, (1) 6a. 1 0 1 0 dbr,aa+3-1 bytes 3-1 0 12 for 32-bit data) 6. 1 0 1 0 dbr,aa byte 0 0 (asl,rol, lsr, ror 2. 1 1 0 1 pbr,pc+1 aal 1 dec, inc, tsb, trb) 3. 1 1 0 1 pbr,pc+2 aah 1 (6 opcodes) 4. 1 0 1 0 dbr,aa byte 0 1 (3 bytes) (1) 4a. 1 0 1 0 dbr,aa+-3 bytes 1-3 1 (6 for 8-bit data, (3) 5. 1 0 0 0 dbr,aa+1 or 3 10 1 2c. absolute (jump)-a 1. 1 1 1 1 pbr,pc opcode 1 (jmp) (4c) 2. 1 1 0 1 pbr,pc+1 new pcl 1 (1 opcode) 3. 1 1 0 1 pbr,pc+2 new pch 1 (3 bytes) 1. 1 1 1 1 pbr,new pc new opcode 1 (3 cycles) 2d. absolute (jump to 1. 1 1 1 1 pbr,pc opcode 1 (3 bytes) 5. 1 1 1 0 o,s pch 0 (6 cycles) 6. 1 1 1 0 o,s-l pcl 0 subroutine)-a 2. 1 1 0 1 pbr,pc+l new pcl 1 (jsr) 3. 1 1 0 1 pbr,pc+2 new pch 1 (1 opcode) 4. 1 1 0 0 pbr,pc+2 10 1 (different order from 1. 1 1 1 1 pbr,new pc new opcode 1 n6502) *3a. absolute long-al 1. 1 1 1 1 pbr,pc opcode 1 (ora, and, eor,adc 2. 1 1 0 1 pbr, pc+1 aal 1 sta,lda,cmp,sbc) 3. 1 1 0 1 pbr,pc+2 aah 1 (8 opcodes) 4. 1 1 0 1 pbr,pc+3 aab 1 (5, 6 and 8 cycles) (1) sa. 1 1 1 0 aab,aa+1 bytesl-3 1/0 *3b. absolute long (jump)-al 1. 1 1 1 1 pbr,pc opcode 1 (4 bytes) 5. 1 1 1 0 aab,aa byte 0 1/0 (jmp) 2. 1 1 0 1 pbr,pc+1 new pcl 1 (1 opcode) 3. 1 1 0 1 pbr,pc+2 new pch 1 (4 bytes) 4. 1 1 0 1 pbr,pc+3 new'br 1 (4 cycles) 1. 1 1 1 1 new pbr,pc opcode 1 march 1990 34 wdc the western design ~enter, inc. w65c832 address mode cycle vp,ml,vda,vpa address bus data bus r/w *3c. absolute long (jump to 1. 1 1 1 1 pbr,pc opcode 1 subroutine long)-al 2. 1 1 a 1 pbr,pc+1 new pcl 1 (jsl) 3. 1 1 0 1 pbr,pc+2 new pch 1 (1 opcode) 4. 1 1 1 a a,s pbr a (4 bytes) 5. 1 1 a a o,s io 1 (7 cycles) 6. 1 1 0 1 pbr,pc+3 new pbr 1 7. 1 1 1 0 o,s-l pch a 8. 1 1 1 0 o,s-2 pcl 0 4a. direct-d (bit,stz,sty,ldy, 1. 1. 2. 1 1 1 1 1 1 1 1 0 1 1 1 new pbr,pc pbr,pc pbr,pc+1 new opcode opcode do 1 1 1 cpy,cpx,stx,ldx, (2) 2a. 1 1 a 0 pbr,pc+1 io 1 ora, and, eor,adc, 3. 1 1 1 0 o,d+do byte a 1/0 sta,lda,cmp,sbc) (18 opcodes) (1) 3a. 1 1 1 0 o ,d+do+1-3 bytesl-3 1/0 (2 bytes) 4b. (3, 4, direct 5 and 7 cycles) (r-m-w)-d 1. 1 1 1 1 pbr,pc opcode 1 (asl, rol, lsr, ror 2. 1 1 a 1 pbr, pc+1 do 1 dec,inc,tsb,trb) (2) 2a. 1 1 a 0 pbr,pc+l io 1 (6 opcodes) 3. 1 0 1 0 o,d+do byte 0 1 (2 bytes) (5,6,7,8,11 and 12 cycles) (1) (3) (1) 3a. 4. sa. 1 1 1 0 0 0 1 0 1 0 0 0 o,d+do+1-3 o,d+do+1 or o,d+do+3-1 3 bytes 1-3 io bytes 3-1 1 1 0 5. 1 0 1 0 o,d+do byte 0 0 5. accumulator-a (asl,inc,rol,dec,lsr,ror) 1. 2. 1 1 1 1 1 0 1 0 pbr, pc pbr,pc+l opcode io 1 1 (6 opcodes) 6a. (1 byte) ( 2 cycles) implied i (dey,iny,inx,dex,nop, 1. 2. 1 1 1 1 1 0 1 0 pbr,pc pbr,pc+1 opcode io 1 1 xce,tya,tay,txa,txs, tax,tsx,tcs,tsc,tcd, tdc,txy,tyx,clc,sec, cli,sei,clv,cld,sed) (25 opcodes) (1 byte) (2 cycles) *6b. implied i 1. 1 1 1 1 pbr,pc opcode 1 (xba) 2. 1 1 0 0 pbr,pc+1 io 1 (1 opcode) 3. 1 1 0 0 pbr,pc+1 10 1 (1 byte) (3 cycles) f6c. wait-for-interrupt roy (wai) 1. 1 1 1 1 1 pbr, pc opcode 1 (1 opcode) ( 9) 2. 1 1 0 0 1 pbr,pc+1 10 1 (1 byte) 3. 1 1 0 0 0 pbr,pc+1 10 1 (3 cycles) irq, nmi 1. 1 1 1 1 1 pbr,pc+1 irq (brk) 1 march 1990 35 woc the western design center, inc. w65c832 address mode cycle vp,ml,vda,vpa address bus data bus r/n #6d. stop-the-clock (stp) (1 opcode) (1 byte) res-=l 1. 2. 3. 1 1 1 1 1 1 1 0 0 roy 1 1 0 1 0 1 pbr,pc pbr,pc+1 pbr,pc+1 opcode 10 10 1 1 1 (3 cycles) res-=o res-=o res-=l 1c. lb. 1a. 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 pbr,pc+1 pbr,pc+1 pbr,pc+1 res (brk) res (brk) res (brk) 1 1 1 (see 21a. stack 1. 1 1 1 1 1 pbr,pc+1 begin 1 hardware interrupt) 7. direct indirect indexed-(d),y 1. 2. 1 1 1 1 1 0 1 1 pbr,pc pbr,pc+1 opcode do 1 1 (ora,and,eor,adc, (2) 2a. 1 1 0 0 pbr,pc+1 io 1 sta,lda,cmp,sbc) (8 opcodes) (2 bytes) (4) 3. 4. 4a. 1 1 1 1 1 1 1 1 0 0 0 0 o,d+do 0,d+do+1 dbr,aaj,aal+yl aal aah 10 1 1 1 (5,6,7,8,9 and 10 5. 1 1 1 0 dbr,aa+y byte 0 1/0 cycles) (1) sa. 1 1 1 0 dbr,aa+y+1-3 bytesl-3 1/0 8. direct indirect indexed long-(d],y (ora, and, eor, adc, (2) 1. 2. 2a. 1 1 1 1 1 1 1 0 0 1 1 0 pbr,pc pbr,pc+1 pbr,pc+1 opcode do 10 1 1 1 sta, lda, cmp, sbc) 3. 1 1 1 0 o,d+do aal 1 (8 opcodes) (2 bytes) (6,7,8,9 and 10 (17) 4. 5. sa. 1 1 1 1 1 1 1 1 0 0 0 0 0,d+do+1 0,d+do+2 0,0+do+2 aah aab 10 1 1 1 cycles) 9. direct indexed indirect-(d,x) (1) 6. 6a. 1. 2. 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 aab,aa+y aab,aa+y+1-3 pbr,pc pbr,pc+1 byte 0 1/0 bytesl-3 1/0 opcode 1 do 1 (ora,and,eor,adc, (2) 2a. 1 1 0 0 pbr,pc+1 10 1 sta,lda,cmp,sbc) (8 opcodes) (2 bytes) 3. 4. 5. 1 1 1 1 1 1 0 1 1 0 0 0 pbr,pc+1 o,d+do+x o,d+do+x+1 10 aal aah 1 1 1 (6,7,8,9 and 10 cycles) (1) 10a.direct,x-d,x (bit,stz,sty,ldy, 6. 6a. 1. 2. 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 dbr,aa dbr,aa+1-3 pbr,pc pbr,pc+1 byte 0 1/0 bytesl-3 1/0 opcode 1 do 1 ora, and, eor,adc, (2 ) 2a. 1 1 0 0 pbr,pc+1 io 1 sta,lda,cmp,sbc) (11 opcodes) (2 bytes) (4,5,6,7 and 8 cycles) (1) 3. 4. 4a. 1 1 1 1 1 1 0 1 1 0 0 0 pbr,pc+1 o,d+do+x 0,d+do+x+1 10 1 byte 0 1/0 bytesl-3 1/0 10b.direct,x(r-m-w)-d,x (asl,rol,lsr,ror, 1. 2. 1 1 1 1 1 0 1 1 pbr,pc pbr,pc+1 opcode do 1 1 dec,inc) (2) 2a. 1 1 0 0 pbr,pc+1 10 1 (6 opcodes) 3. 1 1 0 0 pbr,pc+1 10 1 (2 bytes) (6,7,8,9,12 and 13 cycles) 4. (1) 4a. (3) 5. (1), 6a. 6. 1 1 1 1 1 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 o,d+do+x o,d+do+x+1 0,d+do+x+1 o,d+do+x+1 o,d+do+x byte 0 bytesl-3 10 bytes 3-1 byte 0 1 1 1 0 0 march 1990 36 wdc tae western design center, inc. w65c832 address mode cycle vp,ml,vda,vpa address bus data bus r/w 11. direct,y-d,y (stx, ldx) (2 opcodes) (2) 1. 2. 2a. 1 1 1 1 1 1 1 0 0 1 1 0 pbr,pc pbr,pc+1 pbr,pc+l opcode do 10 1 1 1 (2 bytes) 3. 1 1 0 0 pbr,pc+1 10 1 ( 4, 5, 6, 7 and 8 cycles) 12a.absolute,x-a,x (bit,.ldy, stz, (1) 4. 4a. l. 2. 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 o,d+do+y o,d+do+y+1-3 pbr,pc pbr, pc+l byte 0 1/0 bytesl-3 1/0 opcode 1 aal 1 ora,and, eor,adc, 3. 1 1 0 1 pbr,pc+2 aah 1 sta,lda,cmp,sbc) (11 opcodes) (3 bytes) (4) (1) 3a. 4. 4a. 1 1 1 1 1 1 0 1 1 0 0 0 dbr,aah,aal+xl dbr,aa+x dbr,aa+x+l-3 10 1 byte 0 1/0 bytesl-3 1/0 (4,5,6, 7 and 8 cycles) 12b.absolute,x(r-m-w)-a,x (asl,rol,lsr,ror, l. 2. 1 1 1 1 1 0 1 1 pbr,pc pbr,pc+1 opcode aal 1 1 dec, inc) 3. 1 1 0 1 pbr,pc+2 aah 1 (6 opcodes) 4. 1 1 0 0 dbr,aah,aal+xl 10 1 (3 bytes) (7,9 and 13 cycles) (1) 5. sa. 1 1 0 0 1 1 0 0 dbr,aa+x dbr,aa+x+1-3 byte 0 bytes 1-3 1 1 (3) 6. 1 0 0 0 dbr,aa+x+1or3 io 1 (1) 7a. 1 0 1 0 dbr,aa+x+3-1 bytes 3-1 0 *13. absolute long,x-al,x (ora, and, eor, adc, 7. l. 2. 1 1 1 0 1 1 1 1 0 0 1 1 dbr,aa+x pbr,pc pbr,pc+1 byte 0 opcode aal 0 1 1 sta,lda,cmp,sbc) 3. 1 1 0 1 pbr,pc+2 aah 1 (8 opcodes) 4. 1 1 0 1 pbr,pc+3 aab 1 (4 bytes) (17) 4a. 1 1 0 0 pbr,pc+3 10 1 (5,6,7 and 8 cycles) 5. 1 1 1 0 aab,aa+x byte 0 1/0 14. absolute,y-a,y (ldx,ora/and,eor/adc, sta,lda/cmp/sbc) (1) sa. l. 2. 3. 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 aab,aa+x+1-3 pbr,pc pbr / pc+1 pbr,pc+2 bytesl-3 1/0 opcode 1 aal 1 aah 1 (9 opcodes) (4) 3a. 1 1 0 0 dbr, aah, aal+y 10 1 (3 bytes) (4,5 / 6,7 and 8 cycles) 15. relative-r (bpl,bmi,bvc,bvs/bcc, (1) 4. 4a. l. 2. 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 dbr,aa+y dbr / aa+y+1-3 pbr,pc pbr,pc+1 byte 0 110 bytesl-3 1/0 opcode 1 off 1 bcs,bne,beq,bra) (9 opcodes) (5) (6) 2a. 2b. 1 1 1 1 0 0 0 0 pbr,pc+1 pbr,pc+1 10 10 1 1 (2 bytes) l. 1 1 1 1 pbr,pc+offset opcode 1 (2,3 and 4 cycles) *16. relative long-rl (brl) (1 opcode) (3 bytes) l. 2. 3. 4. 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 0 pbr,pc pbr / pc+1 pbr / pc+2 pbr,pc+2 opcode off low off high 10 1 1 1 1 (4 cycles) - l. 1 1 1 1 pbr,pc+offset opcode 1 17a.absolute indirect-(a) l. 1 1 1 1 pbr,pc opcode 1 (jmp) 2. 1 1 0 1 pbr,pc+1 aal 1 (1 opcode) 3. 1 1 0 1 pbr, pc+2 aah 1 (3 bytes) 4. 1 1 1 0 o,aa new pcl 1 (5 cycles) 5. 1 1 1 0 o/aa+1 new pch 1 l. 1 1 1 1 pbr/new pc opcode 1 march 1990 37 woc the western design center, inc. w65c832 address mode cycle vp,ml,vda,vpa adoress bus oata bus r/w *17b.absolute indirect-(a) 1. 1 1 1 1 pbr,pc opcode 1 (jml) 2. 1 1 0 1 pbr,pc+1 aal 1 (1 opcode) 3. 1 1 0 1 pbr,pc+2 aah 1 (3 bytes) 4. 1 1 1 0 o,aa new pcl 1 (6 cycles 5. 1 1 1 0 o,aa+l new pch 1 6. 1 1 1 0 o,aa+2 new pbr 1 1. 1 1 1 1 new pbr,pc opcode 1 u8. oirect indirect-(d) 1. 1 1 1 1 pbr,pc opcode 1 (ora, and, eor,adc, 2. 1 1 0 1 pbr,pc+1 00 1 sta,loa,cmp,sbc) (2 ) 2a. 1 1 0 0 pbr,pc+1 10 1 (8 opcodes) 3. 1 1 1 0 0,0+00 aal 1 (2 bytes) 4. 1 1 1 0 0,0+00+1 aah 1 *19. (5,6,7,8 and 9 cycles) (1) direct indirect long-[d] 5. sa. 1. 1 1 1 1 1 1 1 1 1 0 0 1 obr,aa pbr,aa+l-3 pbr,pc byte 0 1/0 bytesl-3 1/0 opcode 1 (ora,ano,eor,aoc 2. 1 1 0 1 pbr, pc+l do 1 sta, loa, cmp, sbc (2) 2a. 1 1 0 0 pbr,pc+1 10 1 (8 opcodes) 3. 1 1 1 0 0,0+00 aal 1 (2 bytes) 4. 1 1 1 0 0,0+00+1 aah 1 (6,7,8,9 and 10 cycles) 5. 1 1 1 0 0,0+00+2 aab 1 6. 1 1 1 0 aab,aa byte 0 1/0 20a.absolute (1) indexed indirect- 6a. 1 1 1 0 aab,aa+l-3 bytesl-3 1/0 (a, xl (jmp) 1. 2. 1 1 1 1 1 0 1 1 pbr,pc pbr-pc+l opcode aal 1 1 (1 opcode) 3. 1 1 0 1 pbr-pc+2 aah 1 (3 bytes) 4. 1 1 0 0 pbr,pc+2 10 1 (6 cycles) 5. 1 1 0 1 pbr,aa+x new pcl 1 6. 1 1 0 1 pbr,aa+x+1 new pch 1 1. *20b.absolute indexed indirect- 1. (a, x) 2. 1 1 1 1 1 1 1 1 0 1 1 1 pbr,new pc pbr,pc pbr,pc+1 opcode opcode aal 1 1 1 (jsr) 3. 1 1 1 0 o,s pch 0 (1 opcode) 4. 1 1 1 0 o,s-l pcl 0 (3 bytes) 5. 1 1 0 1 pbr,pc+2 aah 1 (8 cycles) 6. 1 1 0 0 pbr,pc+2 10 1 7. 1 1 0 1 pbr,aa+x new pcl 1 8. 1 1 0 1 pbr,aa+x+l new pch 1 21a.stack (hardware 1. 1. 1 1 1 1 1 1 1 1 pbr,new pc pbr,pc new opcode 1 10 1 interrupts)-s (3) 2. 1 1 0 0 pbr,pc 10 1 (irq,nmi,abort,res) (7) 3. 1 1 1 0 o,s pbr 0 (4 hardware interrupts) (10)4. 1 1 1 0 o,s-l pch 0 (0 bytes) (10) 5. 1 1 1 0 0,s-2 pcl 0 (7 and 8 cycles) (10) (11) 6. 1 1 1 0 o,s-3 p 0 7. 0 1 1 0 o,va aavl 1 8. 0 1 1 0 o,va+1 aavh 1 l. 1 1 1 1 o,aav new opcode 1 march 1990 38 wdc the western design center, inc. w65c832 address mode cycle vp,ml,vda,vpa address bus data bus r/w 21b.stack (software ( 16) 1. 1 1 1 1 pbr,pc opcode 1 (brk,cop) (7) 3. 1 1 1 0 o,s pbr 0 (2 opcodes) 4. 1 1 1 0 o,s-1 pch 0 (2 bytes) 5. 1 1 1 0 o,s-2 pcl 0 (7 and 8 cycles) 6. 1 1 1 0 o,s-3 (16) p 0 interrupts)-s (16) (3) 2. 1 1 0 1 pbr,pc+1 signature 1 7. 0 1 1 0 o,va aavl 1 8. 0 1 1 0 o,va+1 aavh 1 1. 1 1 1 1 o,aav new opcode 1 21c.stack (return from 1. 1 1 1 1 pbr,pc opcode 1 interrupt)-s 2. 1 1 0 0 pbr,pc+1 10 1 (rti) (3) 3. 1 1 0 0 pbr,pc+1 10 1 (1 op code) 4. 1 1 1 0 0, s+1 p 1 (1 byte) 5. 1 1 1 0 o,s+2 pcl 1 (6 and 7 cycles) 6. 1 1 1 0 o,s+3 pch 1 (different order from (7) 7. 1 1 1 0 o,s+4 pbr 1 n6502) 1. 1 1 1 1 pbr,pc new opcode 1 21d.stack (return from 1. 1 1 1 1 pbr/pc opcode 1 subroutine)-s 2. 1 1 0 0 pbr,pc+1 10 1 (rts) 3. 1 1 0 0 pbr,pc+1 10 1 (1 op code) 4. 1 1 1 0 0,s+1 pcl 1 (1 byte) 5. 1 1 1 0 0,s+2 pch 1 (6 cycles) 6. 1 1 0 0 new pc-1 10 1 1. 1 1 1 1 pbr,pc opcode 1 *21e.stack (return from 1. 1 1 1 1 pbr, pc opcode 1 subroutine long)-s 2. 1 1 0 0 pbr,pc+1 io 1 (rtl) 3. 1 1 0 0 pbr,pc+1 10 1 (1 op code) 4. 1 1 1 0 0, s+1 new pcl 1 (1 byte) 5. 1 1 1 0 0,s+2 new pch 1 (6 cycles) 6. 1 1 1 0 0/s+3 new pbr 1 1. 1 1 1 1 new pbr,pc new opcode 1 21f.stack (push)-s 1. 1 1 1 1 pbr/pc opcode 1 (php/pha,phy,phx, 2. 1 1 0 0 pbr / pc+1 10 1 phd,phk,phb) (1) (11) 3a. 1 1 1 0 o,s bytes3-1 1 (7 op codes) 3. 1 1 1 0 0,s-1-3 by teo 1 (1 byte) 1 (3,4, and 6 cycles) 21g.stack (pull)-s 1. 1 1 1 1 pbr,pc opcode 1 (plp/pla,ply,plx,pld,plb) 2. 1 1 0 0 pbr,pc+1 10 1 (different than n6502) 3. 1 1 0 0 pbr,pc+1 10 1 (6 op codes) 4. 1 1 1 0 0, s+1 byte 0 1 (1 byte) (1) 4a. 1 1 1 0 0,s+2-4 bytes1-3 1 (4,5 and 7 cycles) *21h.stack (push effective 1. 1 1 1 1 pbr,pc opcode 1 indirect address)-s 2. 1 1 0 1 pbr,pc+1 do 1 (pel) (2) 2a. 1 1 0 0 pbr,pc+1 10 1 (1 op code) 3. 1 1 1 0 0,0+00 aal 1 (2 bytes) 4. 1 1 1 0 0,0+00+1 aah 1 (6 and 7 cycles) 5. 1 1 1 0 o,s-1 aah 0 6. 1 1 1 0 0,s-1 aal 0 march 1990 39 wdc the western design center, inc. w65c832 address mode cycle vp,ml,vda,vpa address bus data bus r/w *21i.stack (push effective 1. 1 1 1 1 pbr,pc opcode 1 (lop code) 4. 1 1 1 0 o,s aah 0 (3 bytes) 5. 1 1 1 0 o,s-l aal 0 (5 cycles) absolute address)-s 2. 1 1 0 1 pbr,pc+l aal 1 (pea) 3. 1 1 0 1 pbr,pc+2 aah 1 *21j.stack (push effective 1. 1 1 1 1 pbr, pc opcode 1 (1 op code) 5. 1 1 1 0 o,s pch+off+ 0 (3 bytes) carry (6 cycles) 6. 1 1 1 0 o,s-1 pcl+off 0 program counter relative 2. 1 1 0 1 pbr,pc+1 off low 1 address)-s 3. 1 1 0 1 pbr,pc+2 off high 1 (per) 4. 1 1 0 0 pbr,pc+2 io 1 *22. stack relative-d,s 1. 1 1 1 1 pbr,pc opcode 1 (8 op codes) 4. 1 1 1 0 o,s+so byte 0 1/0 (4,5 and 7 cycles) (ora, and, eor, adl, 2. 1 1 0 1 pbr,pc+1 so 1 sta,lda,cmp,sbc) 3. 1 1 0 0 pbr,pc+1 io 1 (2 bytes) (1) 4a. 1 1 1 0 0,s+so+1-3 bytesl-3 1/0 *23. stack relative indirect 1. 1 1 1 1 pbr,pc opcode 1 indexed-(d,s),y 2. 1 1 0 1 pbr,pc+1 so 1 (ora,and,eor,adc,sta,lda, 3. 1 1 0 0 pbr+pc+1 io 1 cmp, sbc) 4. 1 1 1 0 o,s+so aal 1 (8 op codes) 5. 1 1 1 0 o,s+so+l aah 1 (2 bytes) 6. 1 1 0 0 o,s+so+1 io 1 (7,8 and 10 cycles) 7. 1 1 1 0 dbr,aa+y byte 0 1/0 (1) 7a. 1 1 1 0 dbr,aa+y+1-3 bytesl-3 1/0 - *24a.block move positive i 1. 1 1 1 1 pbr,pc opcode 1 (3 bytes) by tel 5. 1 1 1 0 dba,y dest data 0 x=source address (forward)-xyc (18) i 2. 1 1 0 1 pbr,pc+1 dba 1 (mvp) (18) i 3. 1 1. 0 1 pbr,pc+2 sba 1 (lop code) n-2! 4. 1 1 1 0 sba,x src data 1 (5 and 7 cycles) c=21 6. 1 1 0 0 dba,y io 1 i 7. 1 1 0 0 dba,y io 1 - y=destination i 1. 1 1 1 1 pbr,pc opcode 1 c=iof bytes to move-1(18) i 2. 1 1 0 1 pbr,pc+1 dba 1 x,y decrement (18) i 3. 1 1 0 1 pbr, pc+2 sba 1 mvp is used when the n-11 4. 1 1 1 0 sba,x-1 src data 1 dest. start address by tel 5. 1 1 1 0 dba,y-1 dest data 0 is higher (more c=l, 6. 1 1 0 0 dba,y-1 io 1 positive) than the source i 7. 1 1 0 0 dba,y-1 io 1 - start address. i 1. 1 1 1 1 pbr,pc op code 1 ffffff (18) i 2. 1 1 0 1 pbr,pc+1 dba 1 "- dest start (18) i 3. 1 1 0 1 pbr,pc+2 sba 1 n by tel 4. 1 1 1 0 sba,x-2 src data 1 , source start last' 5. 1 1 1 0 dba,y-2 dest data 0 i -':=dest end c=oi 6. 1 1 0 0 dba,y-2 io 1 , i source end i 7. 1 1 0 0 dba,y-2 io 1 000000 i 1. 1 1 1 1 pbr,pc+3 new opcode 1 march 1990 40 wdc the western design center, inc. w65c832 address mode cycle vp,ml,vda,vpa address bus data bus r!w - *24b.block move negative i l. 1 1 1 1 pbr,pc opcode 1 (backward)-xyc (18) i 2. 1 1 0 1 pbr,pc+1 dba 1 (mvn) (1s) i 3. 1 1 0 1 pbr,pc+2 sba 1 (lop code) n-21 4. 1 1 1 0 sba,x src data 1 (3 bytes) by tel 5. 1 1 1 0 dba,y dest data 0 (7 cycles) c=21 6. 1 1 0 0 dba,y io 1 i 7. 1 1 0 0 dba,y io 1 x=source address y=destination i 1 1 1 1 pbr,pc opcode 1 c=tof bytes to move-l(18) i 2. 1 1 0 1 pbr,pc+l dba 1 x,y increment (18) i 3. 1 1 0 1 pbr,pc+2 sba 1 mvn is used when the n-ll 4. 1 1 1 0 sba,x+l src data 1 dest. start address by tel 5. 1 1 1 0 dba, y+l dest data 0 is lower (more c=ll 6. 1 1 0 0 dba,y+l io 1 negative) than the source i 7. 1 1 0 0 dba,y+l io 1 start address. - i l. 1 1 1 1 pbr,pc opcode 1 fffff (18) i 2. 1 1 0 1 pbr,pc+l dba 1 i source end (18) i 3. 1 1 0 1 pbr,pc+2 sba 1 i i n by tel 4. 1 1 1 0 sba,x+2 src data 1 i i dest.end c=oi 5. 1 1 1 0 dba,y+2 dest data 0 1 i -1- source start i 6. 1 1 0 0 dba,y+2 io 1 v i -dest.start i 7. 1 1 0 0 dba,y+2 io 1 000000 i l. 1 1 1 1 pbr,pc+3 new opcode 1 1. add 1 byte (for immediate only) for 16-bit data, add 3 bytes for 32-bit data, add 1 cycle for 16-bit data and 3 cycles for 32-bit data. 2. add 1 cycle for direct register low (dl) not equal o. 3. special case for aborting instruction. this is the last cycle which may be aborted or the status, pbr or dbr registers will be updated. 4. add 1 cycle for indexing across page boundaries, or write, or 16-bit or 32-bit index registers. when 8-bit index registers or in the emulation mode, this cycle contains invalid addresses. 5. add 1 cycle if branch is taken. 6. add 1 cycle if branch is taken across page boundaries in 6502 emulation mode. 7. subtract 1 cycle for 6502 emulation mode. 8. add 1 cycle for rep, sep. 9. wait at cycle 2 for 2 cycles after nmi- or irq- active input. 10. r/w- remains high during reset. 11. brk bit 4 equals "0" in emulation mode. 12. php and plp. 13. some opcodes shown are not on the w65c02. 14. vda and vpa are not valid outputs on the w65c02 but are valid on the w65c832. the two signals, vda and vpa, are included to point out the upward compatibility to the w65c832. when vda and vpa are both a one level, this is equivalent to sync being a one level. 15. the pbr is not on the w65c02. 16. co-processors may monitor the signature byte to aid in processor to co-processor communications. 17. add 1 cycle for 32-bit index register mode. 18. subtract 2 bytes and 2 cycles when in w65c832 native mode for mvn and mvp. 41 march 1990 wdc the western design center, inc. w65c832 aab absolute address bank aah absolute address high aal absolute address low aavh absolute address vector high aavl absolute address vector low byte 0 data byte 0 bytes 1-3 data bytes 1-3 c accumulator d direct register dba destination bank address dbr data bank register dest destination do direct offset ido immediate data byte 0 idl-3 immediate data bytes 1-3 10 internal operation * = new w65c816/802 addressing modes * = new w65c02 addressing modes blank = nmos 6502 addressing modes off p pbr pc pch pcl r-m-w s sba src so va x,y offset status register program bank register program counter program counter high program counter low read-modify-write stack address source bank address source stack offset vector address index register march 1990 42 i i i i i i i i i i i i i i i i i i i i i i i i i i i i i i woc the western design center, inc. w65c832 section 7 recommended assembler syntax standards 7.1 directives assembler directives are those parts of the assembly language source program which give directions to the assembler; this includes the definition of data area and constants within a program. this standard excludes any definitions of assembler directives. 7.2 comments an assembler should provide a way to use any line of the source program as a comment. the recommended way of doing this is to treat any blank line, or any line that starts with s semi-colon or an asterisk as a comment. other special characters may be used as well. 7.3 the source line any line which causes the generation of a single machine language instruction should be divided into four fields: a label field, the operation code, the operand, the comment field. 7.3.1 the label field--the label field begins in column one of the line. a label must start with an alphabetic character, and may be followed by zero or more alphanumeric characters. an assembler may define an upper limit on the number of characters that can be in a label, so long as that upper limit is greater than or equal to six characters. an assembler may limit the alphabetic characters to upper-case characters if desired. if lower-case characters are allowed, they should be treated as identical to their upper-case equivalents. other characters may be allowed in the label, so long as their use does not conflict with the coding of operand fields. 7.3.2 the operation code field--the operation code shall consist of a three character sequence (mnemonic) from table 6-2. it shall start no sooner than column 2 of the line, or one space after the label if a label is coded. 7.3.2.1 many of the operation codes in table 6-2 have duplicate mnemonics; when two or more machine language instruction have the same mnemonic, the assembler resolves the difference based on the operand. 7.3.2.2 if an assembler allows lower-case letters in labels, it must also allow lower-case letters in the mnemonic. when lower-case letters are used in the mnemonic, they shall be treated as equivalent to the upper-case counterpart. thus, the mnemonics lda, ida and lda must all be recognized, and are equivalent. 7.3.2.3 in addition to the mnemonics shown in table 6-2, an assembler may provide the alternate mnemonics show in table 7-3-1. march 1990 43 wdc the western design center, inc. w65c832 table 7-3-1 alternate mnemonics standard bcc bcs cmp a dec a inc a jsl jml tcd tcs tdc tsc xba alias blt bge cma dea ina jsr jmp tad tas tda tsa swa 7.3.2.4 jsl should be recognized as equivalent to jsr when it is specified with a long absolute address. jml is equivalent to jmp with long addressing forced. 7.3.3 the operand field--the operand field may start no sooner than one space after the operation code field. the assembler must be capable of at least twenty-four bit address calculations. the assembler should be capable of specifying addresses as labels, integer constants, and hexadecimal constants. the assembler must allow addition and subtraction in the operand field. labels shall be recognized by the :eact that they start alphabetic characters. decimal numbers shall be recognized as containing only the decimal digits 0 ... 9. hexadecimal constants shall be recognized by prefixing the constant with a "$" character, followed by zero or more of either the decimal digits or the hexadecimal digits "a" ... "f". if lower-case letters are allowed in the label field, then they shall also be allowed as hexadecimal digits. 7.3.3.1 all constants, no matter what their format, shall provide at least enough precision to specify all values that can be represented by a twenty-four bit signed or unsigned integer represented in two's complement notation. 7.3.3.2 table 7-3-2 shows the operand formats which shall be recognized by the assembler. the symbol d is a label or value which the assembler can recognize as being less than $100. the symbol a is a label or value which the assembler can recognize as greater than $ff but less than $10000; the symbol al is a label or value that the assembler can recognize as being greater than $fff. the symbol ext is a label which cannot be located by the assembler at the time the instruction is assembled. unless instructed otherwise, an assembler shall assume that ext labels are two bytes long. the symbols rand rl are 8 and 16 bit signed displacements calculated by the assembler. -- 7.3.3.3 note that the operand does not determine whether or not immediate address loads one or two bytes, this is determined by the setting of the status register. this forces the requirement for a directive or directives that tell the assembler to generate one or two bytes of space for immediate loads. the directives provided shall allow separate settings for the accumulator and index registers. march 1990 44 wdc the western design center, inc. w65c832 7.3.3.4 the assembler shall use the <, >, and characters after the #: a character in immediate address to specify which byte or bytes will be selected from the value of the operand. any calculations in the operand must be performed before the byte selection takes place. table 7-3-2 defines the action taken by each operand by showing the effect of the operator on an address. the column that shows a two byte immediate value show the bytes in the order in which they appear in memory. the coding of the operand is for an assembler which uses 32 bit address calculations, showing the way that the address should be reduced to a 24 bit value. table 7-3-2 byte selection operator operand one byte result two byte result four byte result #$01020304 04 03 04 01 02 03 04 #<$01020304 04 03 04 #>$01020304 03 02 03 1"$01020304 02 01 01 7.3.3.5 in any location in an operand where an address, or expression resulting in an address, can be coded, the assembler shall recognize the prefix characters <, i, and >, which force one byte (direct page), two byte (absolute) or three byte (long absolute) addressing. in cases where the addressing modes is not forced, the assembler shall assume that the address is two bytes unless the assembler is able to determine the type of addressing required by context, in which case that addressing mode will be used. addresses shall be truncated without error in an addressing mode is forced which does not require the entire value of the address. for example, lda $0203 lda \$010203- are completely equivalent. if the addressing mode is not forced, and the type of addressing cannot be determined from context,t he assembler shall assume that a two byte address is to be used. if an instruction does not have a short addressing mode (as in lda< which ahs no direct page indexed by y) and a short address is used in the operand, the assembler shall automatically extend the address by padding the most significant bytes with zeroes in order to extend the address to the length needed. as with immediate address, any expression evaluation shall take place before the address is selected; thus, the address selection character is only used once, before the address of expression. 7.3.3.6 the! (exclamation point) character should be supported as an alternative to the i (vertical bar). 7.3.3.7 a long indirect address is indicated in the operand field of an instruction field of an instruction by surrounding the direct page address where the indirect address is found by square brackets; direct page addresses which contain sixteen-bit addresses are indicated by being surrounded by parentheses. 7.3.3.8 the operands of a block move instruction are specified as source bank, destination bank-the opposite order of tzz object bytes generated. 7.3.4 comment field--the comment field may start no sooner than one space after the operation code field or operand field depending on instruction ~ type. /' march 1990 45 wdc the western design center, inc. w65c832 section 8 caveats table 8-1 w65c816 compatibility issues i i w65c816/802 i w65c02 i nmos 6502 11. s (stack) ialways page 1 (e=ialways page l,81always page 1,8 i 11), 8 bits; 16 ibits ibits i ibits when (e=o) i i 12. x (x index reg) iindexed page zerolalways page 0 ialways page 0 i i always in page 0 i i i i (e=l), cross page i i i i (e=o) i i 13. y (y index reg) i indexed page zerolalways page 0 ialways page 0 i i always in page 0 i i i i (e=l), cross page i i i i (e=o) i i 14. a (accumulator) 18 bits (m=l), 16 18 bits 18 bits i ibits (m=o) i i 15. (flag reg) in,v, and z flags in,v, and zflagsln,v, and z flags i i valid in decimal i valid in dec. i invalid in i i i i decimal i i mode. d=o after i mode. d=o after i mode. d=unknown i i reset/interrupt. ireset/interruptlafter reset. d i i i i not modified i i i i after interrupt i 6. timing i i i i a. abs,x asl, lsr, 17 cycles 16 cycles 17 cycles i operand=xxff 15 cycles 16 cycles 15 cycles and i i i i invalid page i i i i crossing 1 c. branch across 14 cycles (e=l) 14 cycles 14 cycles i d. decimal mode ina add. cycle iadd 1 cycle ina add. cycle i rol, ror with no i i i i page crossing i i i lb. jump indirect i i i i page 13 cycles (e=o) i i 17. brk vector 100fffe,f (e=l) ifffe,f brk bit=ifffe,f brk bit=o 1 i ibrk bit=o on 10 on stack if ion stack if irq-, i i istack if irq-, iirq-, nmi-. inmi-. i i inmi-,abort-. i i i i 100ffe6,7 (e=o) x=1 i i i i x on stack always i i i 18. interrupt or break ipbr not pushed inot available inot available i i bank address i (e=l), rti pbr i i i i i not pulled (e=l) , i i i i i pbr pushed (e=o), i i i i 1 rti pbr pulled i i i 1 i (e=o) i i i 19. memory lock (ml-) iml-=o during readiml-=o during inot available i i imodify and write imodify and i i i ________________ ~~----------~--~~----~------------i 46 march 1990 wdc the western design center, inc. w65c832 i w65c8l6/802 i w65c02 nmos 6502 i 10. indexed across page i extra read of iextra read of iextra read of boundary (d),yia,x; i invalid address. ilast instructionlinvalid address. i a,y i (note 1) i fetch. i ill.roy pulled during iignored (e-l) forlprocessor stops. i ignored. i write cycle iw65c816 only. i i i iprocessor stops i i i i (e=o) . i i or. 1:1,2:. wai & stp instruct. i available i available i not available r- 113.unused op codes lone reserved op ino operation. iunknown and some '" i i code specified as i i "hang up" -,. f i wdm will be used i i processor. i i in future systems i ,i i i the w65c816 i i i i performs a no- i i j i operation. i i '(:':-114.bank address lpbr=oo after re- i not available i not available :r:r ';cf '':;handling i set or interrupts i i ;:'?':;l15~; r/w';' during read- i e=l, r/w-=o during i r/w-=o only dur-i r/w-=o during ",,,:,cy::,')m6dify-write imodify and write i ing write cycle. i modify and write pc.l''''p ,;, instructions i cycles. e=o, r/w-= i i cycles. , i i 0 only during i .. 116.pin 7 iw65c802=sync. i sync i sync i ~,[ f';;:'c~/ iwrite cycle. i i ':-~1 .. iw65c816=vpa i i .. 117.cop instruction i available inot available inot available .. i . ,,: signatures 00-7f i i i --'r=' defined. signatures i i i i--~~~~~~~--~------------~------------~-------------- 8.1 stack addressing when in the native mode, the stack may use memory locations 000000 to oofffff. the effective address of stack, stack relative, and stack relative indirect indexed- addressing modes will always be within this range. in the emulation mode, the stack address range is 000100 to ooolff. the following opcodes and addressing modes will increment or decrement beyond this range when accessing two or three bytes. jsl; jsr(a, x); pea, pel, per, phd, pld, rtl; d, si (d, s), y 8.2 direct addressing 8.2.1 the direct addressing modes are often used to access memory registers direct,y addressing modes will always be in the native mode range 000000 000000 to ooooff, except for [direct] and [direct], y addressing modes and the pel instruction which will increment from oooofe or ooooff into the stack area. and pointers. the effective address generated by direct; direct,x and to ooffff. when in the emulation mode, the direct addressing range is march 1990 47 woc the western design center, inc. w65c832 8.2.2 when in the emulation mode and dh is not equal to zero, the direct addressing range is oodhoo to oodhff, except for [direct] and [direct],y addressing modes and the pei instruction which will increment from oodhfe or oodhff into the next higher page. 8.2.3 when in the emulation mode and dl in not equal to zero, the direct addressing range is 000000 to ooffff. 8.3 absolute indexed addressing the absolute indexed addressing modes are used to address data outside the direct addressing range. the w65c02 and w65c832 addressing range is oo(}:o to ffff. indexing from page ffxx may result in a ooyy data fetch when using the w65c02 or w65c832. in contrast, indexing from page zzffxx may result in zz+l,ooyy when using the w65c832. :- i 8.4 abort- input i 8.4.1 abort- should be held low for a period no~to exceed one cyp 1 e!; "also i if abort- is held low during the abort interrupt sequencer: the abort interrupt will be aborted. it is not recommended to. abort.:;the:_~bort interrupt. the abort- internal latch is cleared during the sel?9~d cycle of the abort interrupt. asserting the abort- input after ~1!e ~ollqwing instruction cycles will cause registers to be modified: . 8.4.1.1 read-modify-write: processor status modified if abortt is asserted after a modify cycle. . 8.4.1.2 rti: processor status modified if abort- is asserted"after cycle 3. 8.4.1.3 irq-, nmi -, abort- brri cop: when abort- is asserted' after cycle 2, pbr and dbr will become 00 (emulation mode) or pbrwill become 00 (native mode). 8.4.2 the abort- interrupt has been designed for virtual memory systems. for this reason l asynchronous abort/s- may cause undesirable results due to the above conditions. 8.5 vda and vpa valid memory address output signals when vda or vpa are high and during all write cycles, the address bus is always valid. vda and vpa should be used to qualify all memory cycles. note that when vda and vpa are both low l invalid addresses may be generated. the page and bank addresses could also be invalid. this will be due to low byte addition only. the cycle when only low byte addition occurs is an optional cycle for instructions which read memory when the index register consists of 8 bits. this optional cycle becomes a standard cycle for the store instruction, all instructions using the 16-bit index register mode, and the read-modify-write instruction when using 8- or 16-bit index register modes. 8.6 apple ii, iie l iic and ii+ disk systems vda and vpa should not be used to qualify addresses during disk operation on apple systems. consult your apple representative for hardware/software configurations. 48 march 1990 wdg the western design center, inc. w65c832 8.7 dbiba qperation when roy is pulled low when rdy is low, the data bus is held in the data transfer state (i.e., phi2 high) .'rhe bank address external transparent latch should be latched when the . phi2clo.ek or rdy is .low. 8 !.%' m(x output:. : .. :1.:) ',.: ~"'.s. the mix output reflects the valid of them and x bits of the processor status il ~:re,gis.ter{. the rep, sep and plp .instructions may change the state of the m and x bits. note that the nix output is :invalid. during the instruction cycle following rep, sep and plp instruction execution. this cycle is used as the opcode fetch cycle of the next instruction. ::::: s:-: ,:":'; ,'j::7"',~ .::.. . : - ,:.:; ':' 8.9.1 it should be noted that all opcodes function in all modes of operation. however, some instructions and addressing modes are intended for w65c832 24-bit addressing and are therefore less useful for the w65c832. the kg';: f .? i:ouqwing is a;; list of instructions and addressing modes which are .;,; ,!9:;8r.:'.~::..:; ~:t"t.marily intended for .w65c832 use: j:::od.e ~_ " .!.j jsl;rtl; cd] i cd] ,yijmp alijmlial,al,x 8l'j.r.a;~9 .:?-.:th~:o following .instru~tions may be used with the w65c832 even though a jx91! 5::~ ~~nck ao,dress is not multiplexed on the data bus: 9dj ~~ r~l~' :.phkiphb;plb . :-;f. ~:t9;.~,.l'deot'01lowing instructions have "limited" use in the emulation mode: ... ~ "..... ;.8: 9.3 .. 1 the rep and sep instructions cannot modify the m and x bits when ""~:',l ... in jpe emulation mode. in this mode the m and x bits will always be high .~ .?? ?. .j. ~ ;_~ :~log~c 1). 8.9.3.2 when in the emulation mode, the mvp and mvn instructions use the x and y index registers for the memory address. also, the mvp and mvn illstructions can only move data within the memory range 0000 (source bank) to ooff (destination bank) for the w65c832, and 0000 to ooff for ~' .. -~.:. the ~w65c832. . - 8 .. 19~n~lir~.9t . j~ps : .. ,he jmp (a) ,and jml .(a) instructions use the direct bank for indirect addressing, while jmp (a, x) and jsr (a, x) use the program bank for indirect address tables. 8.11 switching modes 1..:_ ' - .. whe;n switching from the native mode to the emulation mode, the x and m bits of the status register are set high (logic 1), the high byte of the stack is set to 01, and the high bytes of the x and y index registers are set to 00. to save previous values, these bytes must always be stored before changing modes. note that the low byte of the s, x and y registers and the low and high byte of the accumulator (a and b) are not affected by a mode change. 49 march 1990 wdc the western design~center, inc. w65c832, 8.12 how hardware interrupts, brk, and cop instructions affect the program bank and the data bank registers 8.12.1 when in the native mode, the program bank register (pbr) is cleared to 00 when a hardware interrupt, brk or cop is executed. ift' the native mode, previous pbr contents is automatically saved on stack. 8.12.2 in the emulation mode, the pbr and dbr registers are cleared to oo.when i? a hardware interrupt, brk or cop is executed. in this case, previous contents of the pbr are not automatically saved. '., " 8.12.3 note that a ret urn from .,interrupt (rti) should always be executed' '~from the same "mode" which originally ~gem'erated the interrupt~ ~ , 8.13 binary mode the binary mode is set whenever a :tta:tdwitre"'r~,softwate,14..nte~rupt:r-:j,s,)':zexeguted. 8 the d flag within the status register is cleared to zero. j'~~.:":. i:.~jf):'y ::'c.-l ~":_ ... " __ .~: :"'7 l , ~' ,8 8.14 wai instruction the wai instruction pulls rdy low and 'places the p~ocessor ,in' -the wai "low power" mode. nmi-, irq- or reset will termina'te the' wai~.conditiotr alld transfer control to the interrupt handler routine: note that an abort~ input will abort the wai instruction, but will not restart the; processor. when;':the. tstatus register i flag is set (irq- disabled), the irq.:- interrupt will ca1fie the next instruction (following the wai instruction) to be executed without going to the irq- interrupt handler. this method results in the highest' speedtespense~: te an irq- input. when an interrupt is received after an abort- whic~ocaurs during the wai instruction, the processor will return to the 'wai instruction. other than res- (highest priority), abort- is the next highest priority, ~followed by , nmi- or irq- interrupts. ? ~ 8.15 the stp instruction disables the phi2 clock to all circuitry. when disabled, the phi2 clock is held in the high state. in this case, the dta bus will remain in the data transfer state and the bank address will notb~ multiplexed onto the data bus. upon executing the stp instruction, the res- signal is the only input which can restart the processor. the processor 'is . r-e'started 'by t enabling the phi2 clock, which occurs on the falling edge of the res- input. note that the external oscillator must be--stable, and ,operating p'roperly before res- goes high. .. -,. . - , 8.16 cop signatures ':" '., signatures 00-7f may be user defined, while signatures 80-ff are reserved for instructions on future microprocessors:~ ::,c:contact wdc for software-emulation of future microprocessor hardware functio{ls ~, .,[ 8.17 wdm opcode use the wdm opcode will be used on future microprocessors. march 1990 50 wdc the western design center, inc. w65c832 s.18 roy pulled during write the nmos 6502 does not stop during a write operation. in contrast, both the w65c02 and the w65c832 do stop during write operations. the w65c832 stops during a write when in the native mode, but does not stop when in the emulation mode. 8.19 mvn and mvp affects on the data bank register the mvn and mvp instructions change the data bank register to the value of the second byte of the instruction (destination bank address) . 8.20 interrupt priorities the following interrupt priorities will be in effect should more than one interrupt occur at the same time: res- highest priority abort- nmi- irq- lowest priority 8.21 transfers from differing register sizes all transfers from one register to another will result in a full 32-bit output from the source register. the destination register size will determine the number of bits actually stored in the destination register and the values stored in the processor status register. the following are always 16-bit transfers, regardless of the accumulator size: tasitsaitaditda 8.22 stack transfers when in the w65c02 emulation mode, a 01 is forced into the high byte of the 16-bit stack pointer. when in the native mode or w65c816 emulation mode, the a accumulator is transferred to the 16-bit stack pointer. note that in both the emulation and native modes, the full 16 bits of the stack register are transferred to the a accumulator regardless of the state of the m bit in the status register. 8.23 rep/sep wdc had problems using the rep and sep instructions in early versions of the high-speed w65c816 and w65cs02 devices and has been corrected on all w65cs32 devices. march 1990 51 |
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